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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_rpc_in_reg] - Blame information for rev 134

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// shift  buffer and shadow
reg [BITS-1:0]  buffer;
 
always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)
  if (test_logic_reset)                 buffer <= RESET_VALUE;
  else
  if (select && capture_dr)             buffer <= capture_value;
  else
  if (select && shift_dr)               buffer <= { tdi, buffer[BITS-1:1] };
  else                                  buffer <= buffer;
 
 
 
 
 assign tdo = buffer[0];
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`// shift buffer and shadow`
2			`reg [BITS-1:0] buffer;`
3
4			`always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)`
5			`if (test_logic_reset) buffer <= RESET_VALUE;`
6			`else`
7			`if (select && capture_dr) buffer <= capture_value;`
8			`else`
9			`if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };`
10			`else buffer <= buffer;`
11
12
13
14
15			`assign tdo = buffer[0];`
16
17

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_rpc_in_reg] - Blame information for rev 134