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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_sync] - Blame information for rev 134

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   reg                    synced_reset;
 
   always@(posedge clk or posedge test_logic_reset  )
   if(test_logic_reset)
      begin
      synced_reset <= 1'b1;
      syn_reset    <= 1'b1;
      end
   else
      begin
      synced_reset <= test_logic_reset;
      syn_reset    <= synced_reset;
      end
 
 
   reg                    synced_shift_dr;
   reg                    synced_capture_dr;
 
 
 
 
   always@(posedge clk)
     if(!shiftcapture_dr_clk)
       begin
       synced_shift_dr    <= shift_dr ;
       synced_capture_dr  <= capture_dr ;
       end
 
     else
       begin
       synced_shift_dr    <= synced_shift_dr ;
       synced_capture_dr  <= synced_capture_dr ;
       end
 
 
   reg [1:0]  synced_shiftcapture_dr_clk;
 
 
   always@(posedge clk)
     synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};
 
 
   reg [1:0]  synced_update_dr_clk;
 
 
   always@(posedge clk)
     synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};
 
 
 
   always@(posedge clk)
     if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_shift_dr      <= synced_shift_dr ;
       syn_capture_dr    <= synced_capture_dr ;
       end
     else
       begin
       syn_shift_dr      <= 1'b0 ;
       syn_capture_dr    <= 1'b0 ;
       end
 
 
 
   always@(posedge clk)
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_update_dr      <= 1'b1 ;
       end
     else
       begin
       syn_update_dr      <= 1'b0 ;
       end
 
 
 
   always@(posedge clk)
     if(!shiftcapture_dr_clk && (shift_dr || capture_dr  ))
       begin
       syn_tdi_o         <= tdi ;
       end
 
     else
       begin
       syn_tdi_o         <= syn_tdi_o ;
       end
 
 
 
 
 
 
 
 
 
 
   always@(posedge clk)
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_select      <= select;
       end
   else if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_select      <= select;
       end
 
     else
       begin
       syn_select      <= syn_select;
       end
 
 
 
 
 
 
 
 
   assign    syn_clk             = clk;
   assign    tdo                 = syn_tdo_i;
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`reg synced_reset;`
2
3			`always@(posedge clk or posedge test_logic_reset )`
4			`if(test_logic_reset)`
5			`begin`
6			`synced_reset <= 1'b1;`
7			`syn_reset <= 1'b1;`
8			`end`
9			`else`
10			`begin`
11			`synced_reset <= test_logic_reset;`
12			`syn_reset <= synced_reset;`
13			`end`
14
15
16			`reg synced_shift_dr;`
17			`reg synced_capture_dr;`
18
19
20
21
22			`always@(posedge clk)`
23			`if(!shiftcapture_dr_clk)`
24			`begin`
25			`synced_shift_dr <= shift_dr ;`
26			`synced_capture_dr <= capture_dr ;`
27			`end`
28
29			`else`
30			`begin`
31			`synced_shift_dr <= synced_shift_dr ;`
32			`synced_capture_dr <= synced_capture_dr ;`
33			`end`
34
35
36			`reg [1:0] synced_shiftcapture_dr_clk;`
37
38
39			`always@(posedge clk)`
40			`synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};`
41
42
43			`reg [1:0] synced_update_dr_clk;`
44
45
46			`always@(posedge clk)`
47			`synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};`
48
49
50
51			`always@(posedge clk)`
52			`if(synced_shiftcapture_dr_clk == 2'b01)`
53			`begin`
54			`syn_shift_dr <= synced_shift_dr ;`
55			`syn_capture_dr <= synced_capture_dr ;`
56			`end`
57			`else`
58			`begin`
59			`syn_shift_dr <= 1'b0 ;`
60			`syn_capture_dr <= 1'b0 ;`
61			`end`
62
63
64
65			`always@(posedge clk)`
66			`if(synced_update_dr_clk == 2'b01)`
67			`begin`
68			`syn_update_dr <= 1'b1 ;`
69			`end`
70			`else`
71			`begin`
72			`syn_update_dr <= 1'b0 ;`
73			`end`
74
75
76
77			`always@(posedge clk)`
78			`if(!shiftcapture_dr_clk && (shift_dr \|\| capture_dr ))`
79			`begin`
80			`syn_tdi_o <= tdi ;`
81			`end`
82
83			`else`
84			`begin`
85			`syn_tdi_o <= syn_tdi_o ;`
86			`end`
87
88
89
90
91
92
93
94
95
96
97			`always@(posedge clk)`
98			`if(synced_update_dr_clk == 2'b01)`
99			`begin`
100			`syn_select <= select;`
101			`end`
102			`else if(synced_shiftcapture_dr_clk == 2'b01)`
103			`begin`
104			`syn_select <= select;`
105			`end`
106
107			`else`
108			`begin`
109			`syn_select <= syn_select;`
110			`end`
111
112
113
114
115
116
117
118
119			`assign syn_clk = clk;`
120			`assign tdo = syn_tdo_i;`
121
122

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_sync] - Blame information for rev 134