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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [jtag_rpc_reg.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
module
cde_jtag_rpc_reg
#(parameter BITS        = 16,   // number of bits in the register (2 or more)
  parameter RESET_VALUE = 'h0  // reset value of register
  )
 
(
 
 
input  wire   clk,              // clock
input  wire   reset,            // async reset
input  wire   tdi,              // scan-in of jtag_register
input  wire   select,           // '1' when jtag accessing this register 
output wire   tdo,              // scan-out of jtag register
input  wire   update_dr,
input  wire   capture_dr,
input  wire   shift_dr,
input  wire  [BITS-1:0] capture_value,  // value to latch on a capture_dr
output  reg  [BITS-1:0] update_value   // the register 
 
 
);
 
 
 
 
 
// shift  buffer and shadow
reg [BITS-1:0]  buffer;
 
always @(posedge clk or posedge reset)
  if (reset)                            buffer <= RESET_VALUE;
  else
  if (select && capture_dr)             buffer <= capture_value;
  else
  if (select && shift_dr)               buffer <= { tdi, buffer[BITS-1:1] };
  else                                  buffer <= buffer;
 
 
  always @(posedge update_dr  or posedge reset)
   if (reset)                          update_value <= RESET_VALUE;
   else
   if (select)                         update_value <= buffer;
   else                                update_value <= update_value;
 
 
 
 
assign tdo = buffer[0];
 
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22			`module`
23			`cde_jtag_rpc_reg`
24			`#(parameter BITS = 16, // number of bits in the register (2 or more)`
25			`parameter RESET_VALUE = 'h0 // reset value of register`
26			`)`
27
28			`(`
29
30
31			`input wire clk, // clock`
32			`input wire reset, // async reset`
33			`input wire tdi, // scan-in of jtag_register`
34			`input wire select, // '1' when jtag accessing this register`
35			`output wire tdo, // scan-out of jtag register`
36			`input wire update_dr,`
37			`input wire capture_dr,`
38			`input wire shift_dr,`
39			`input wire [BITS-1:0] capture_value, // value to latch on a capture_dr`
40			`output reg [BITS-1:0] update_value // the register`
41
42
43			`);`
44
45
46
47
48
49			`// shift buffer and shadow`
50			`reg [BITS-1:0] buffer;`
51
52			`always @(posedge clk or posedge reset)`
53			`if (reset) buffer <= RESET_VALUE;`
54			`else`
55			`if (select && capture_dr) buffer <= capture_value;`
56			`else`
57			`if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };`
58			`else buffer <= buffer;`
59
60
61			`always @(posedge update_dr or posedge reset)`
62			`if (reset) update_value <= RESET_VALUE;`
63			`else`
64			`if (select) update_value <= buffer;`
65			`else update_value <= update_value;`
66
67
68
69
70			`assign tdo = buffer[0];`
71
72
73			`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [jtag_rpc_reg.v] - Blame information for rev 131