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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_in_reg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
classic_rpc_in_reg  default
 

 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 

 
 
 
 
 
 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

BITS16
RESET_VALUE'h0

 

 
shiftcapture_dr_clk
wire
in

 
test_logic_reset
wire
in

 
 
tdi
wire
in

 
select
wire
in

 
capture_dr
wire
in

 
shift_dr
wire
in

 
 
tdo
wire
out

 
 
capture_value
wire
in
BITS-10

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`classic_rpc_in_reg default`
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31			`fs-sim`
32
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35			`dest_dir`
36			`../verilog/`
37			`verilogSourcelibraryDir`
38
39
40
41
42
43
44			`fs-syn`
45
46
47			`dest_dir`
48			`../verilog/`
49			`verilogSourcelibraryDir`
50
51
52
53
54
55
56
57
58
59			`fs-lint`
60
61			`dest_dir../verilog/`
62			`verilogSourcelibraryDir`
63
64
65
66
67
68
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70
71
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81			`sim:Simulation:`
82			`Verilog`
83
84
85			`fs-sim`
86
87
88
89
90			`syn:Synthesis:`
91			`Verilog`
92
93
94			`fs-syn`
95
96
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99
100
101			`doc`
102
103
104			`spirit:library="Testbench"`
105			`spirit:name="toolflow"`
106			`spirit:version="documentation"/>`
107
108			`:Documentation:`
109			`Verilog`
110
111
112
113
114
115
116
117
118
119
120
121
122			`BITS16`
123			`RESET_VALUE'h0`
124
125
126
127
128			`shiftcapture_dr_clk`
129			`wire`
130			`in`
131
132
133			`test_logic_reset`
134			`wire`
135			`in`
136
137
138
139			`tdi`
140			`wire`
141			`in`
142
143
144			`select`
145			`wire`
146			`in`
147
148
149			`capture_dr`
150			`wire`
151			`in`
152
153
154			`shift_dr`
155			`wire`
156			`in`
157
158
159
160			`tdo`
161			`wire`
162			`out`
163
164
165
166			`capture_value`
167			`wire`
168			`in`
169			`BITS-10`
170
171
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_in_reg.xml] - Blame information for rev 131