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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_in_reg.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
classic_rpc_in_reg  default
 
 
 
 
 
 

 
 
 jtag
  
  
    
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr_clk
        update_dr_clk
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
      
        shiftcapture_dr_clk
        shiftcapture_dr_clk
      
 
 
 
    
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      jtag_classic_rpc_in_reg
    
  

 
 
 
 

 
 
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/classic_rpc_in_reg
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/common/jtag_classic_rpc_in_reg
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/common/jtag_classic_rpc_in_reg
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 

 
 
 
 
 

BITS16
RESET_VALUE'h0

 

 
 
capture_value
wire
in
BITS-10

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_in_reg.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`classic_rpc_in_reg default`
16
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22	134	jt_eaton
23	131	jt_eaton
24
25	134	jt_eaton	`jtag`
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29	131	jt_eaton
30	134	jt_eaton
31			`test_logic_reset`
32			`test_logic_reset`
33
34	131	jt_eaton
35	134	jt_eaton
36			`capture_dr`
37			`capture_dr`
38
39	131	jt_eaton
40	134	jt_eaton
41			`shift_dr`
42			`shift_dr`
43
44	131	jt_eaton
45	134	jt_eaton
46			`update_dr_clk`
47			`update_dr_clk`
48
49	131	jt_eaton
50
51	134	jt_eaton
52			`tdi`
53			`tdi`
54
55	131	jt_eaton
56	134	jt_eaton
57			`tdo`
58			`tdo`
59
60	131	jt_eaton
61	134	jt_eaton
62			`select`
63			`select`
64
65	131	jt_eaton
66
67	134	jt_eaton
68			`shiftcapture_dr_clk`
69			`shiftcapture_dr_clk`
70
71	131	jt_eaton
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74	134	jt_eaton
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76	131	jt_eaton
77	134	jt_eaton
78	131	jt_eaton
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89	134	jt_eaton
90
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102			`gen_verilog`
103			`104.0`
104			`none`
105			`common`
106			`./tools/verilog/gen_verilog`
107
108
109			`destination`
110			`jtag_classic_rpc_in_reg`
111
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126	131	jt_eaton
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130	134	jt_eaton	`verilog`
131
132
133			`spirit:library="Testbench"`
134			`spirit:name="toolflow"`
135			`spirit:version="verilog"/>`
136
137
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142			`commoncommon`
143			`Verilog`
144
145
146			`fs-common`
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154	131	jt_eaton	`sim:Simulation:`
155			`Verilog`
156
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158			`fs-sim`
159
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163			`syn:Synthesis:`
164			`Verilog`
165
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167			`fs-syn`
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174			`doc`
175
176
177			`spirit:library="Testbench"`
178			`spirit:name="toolflow"`
179			`spirit:version="documentation"/>`
180
181			`:Documentation:`
182			`Verilog`
183
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194	134	jt_eaton
195	131	jt_eaton
196
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198	134	jt_eaton
199			`fs-common`
200	131	jt_eaton
201	134	jt_eaton
202
203			`../verilog/classic_rpc_in_reg`
204			`verilogSourcefragment`
205
206	131	jt_eaton
207
208	134	jt_eaton
209
210			`../verilog/copyright`
211			`verilogSourceinclude`
212
213	131	jt_eaton
214
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216	134	jt_eaton
217	131	jt_eaton
218
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220	134	jt_eaton
221
222
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224			`fs-sim`
225
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228
229			`../verilog/common/jtag_classic_rpc_in_reg`
230			`verilogSourcemodule`
231
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235			`dest_dir`
236			`../views/sim/`
237			`verilogSourcelibraryDir`
238
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244			`fs-syn`
245
246
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248			`../verilog/common/jtag_classic_rpc_in_reg`
249			`verilogSourcemodule`
250
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254			`dest_dir`
255			`../views/syn/`
256			`verilogSourcelibraryDir`
257
258
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264
265
266			`fs-lint`
267
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272			`dest_dir../views/syn/`
273			`verilogSourcelibraryDir`
274
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291			`BITS16`
292			`RESET_VALUE'h0`
293
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298	131	jt_eaton	`capture_value`
299			`wire`
300			`in`
301			`BITS-10`
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