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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
classic_rpc_reg
 

 jtag
 
  
  
  
   
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr_clk
        update_dr_clk
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
      
        shiftcapture_dr_clk
        shiftcapture_dr_clk
      
 
 
 
    
        
      
 
 
 
 
  
 
 
 
 
                
                        update_value
                        
                        
                                
                                        
                                        
                                                
                                                        
                                                                adhoc
                                                        
                                                        
                                                                update_value
                                                        
                                                
                                        
                                
                        
                        
                
 
 
                                
                        capture_value
                        
                        
                                
                                        
                                        
                                                
                                                        
                                                                adhoc
                                                        
                                                        
                                                                capture_value
                                                        
                                                
                                        
                                
                        
                        
                
 
 
 
 

 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_classic_rpc_reg
    
  

 
 
 
 

 
 
 
 
 
 

 
                
                        
                                verilog
                                verilog
                                cde_jtag_classic_rpc_reg
                                
                                        
                                                BITS
                                                16
                                        
                                        
                                                RESET_VALUE
                                                16'h0000
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
  
 
                
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
 
               
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 
 
 
 
 

BITS16
RESET_VALUE'h0

 

 
 
 
 
capture_value
wire
in
BITS-10

 
 
update_value
reg
out
BITS-10

 
 
 
test_logic_reset
wire
in


 
 
 
capture_dr
wire
in


 
 
 
shift_dr
wire
in


 
 
 
shiftcapture_dr_clk
wire
in


 
 
 
 
update_dr_clk
wire
in


 
 
tdi
wire
in


 
tdo
wire
out


 
select
wire
in


 
 
 
 
 

 

 
 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/classic_rpc_reg
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/jtag_classic_rpc_reg
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/common/jtag_classic_rpc_reg
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
 
      
        
        ../verilog/common/jtag_classic_rpc_reg
        verilogSourcemodule
      
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`classic_rpc_reg`
16	131	jt_eaton
17	135	jt_eaton
18			`jtag`
19
20
21
22
23
24	131	jt_eaton
25	135	jt_eaton
26			`test_logic_reset`
27			`test_logic_reset`
28
29	131	jt_eaton
30	135	jt_eaton
31			`capture_dr`
32			`capture_dr`
33
34	131	jt_eaton
35	135	jt_eaton
36			`shift_dr`
37			`shift_dr`
38
39	131	jt_eaton
40	135	jt_eaton
41			`update_dr_clk`
42			`update_dr_clk`
43
44	131	jt_eaton
45
46	135	jt_eaton
47			`tdi`
48			`tdi`
49
50	131	jt_eaton
51	135	jt_eaton
52			`tdo`
53			`tdo`
54
55	131	jt_eaton
56	135	jt_eaton
57			`select`
58			`select`
59
60	131	jt_eaton
61
62	135	jt_eaton
63			`shiftcapture_dr_clk`
64			`shiftcapture_dr_clk`
65
66	131	jt_eaton
67
68
69	135	jt_eaton
70
71
72	131	jt_eaton
73
74
75
76	135	jt_eaton
77
78
79	131	jt_eaton
80
81	135	jt_eaton
82			`update_value`
83
84
85
86
87
88
89
90			`adhoc`
91
92
93			`update_value`
94
95
96
97
98
99
100
101	131	jt_eaton
102
103	135	jt_eaton
104			`capture_value`
105
106
107
108
109
110
111
112			`adhoc`
113
114
115			`capture_value`
116
117
118
119
120
121
122
123	131	jt_eaton
124
125	135	jt_eaton
126	131	jt_eaton
127	135	jt_eaton
128	131	jt_eaton
129
130
131	135	jt_eaton
132	131	jt_eaton
133
134
135
136	135	jt_eaton
137			`gen_verilog`
138			`104.0`
139			`none`
140			`:common:`
141			`tools/verilog/gen_verilog`
142
143
144			`destination`
145			`jtag_classic_rpc_reg`
146
147
148
149	131	jt_eaton
150
151
152
153	135	jt_eaton
154	131	jt_eaton
155
156
157
158
159
160	135	jt_eaton
161	131	jt_eaton
162	135	jt_eaton
163
164			`verilog`
165			`verilog`
166			`cde_jtag_classic_rpc_reg`
167
168
169			`BITS`
170			`16`
171
172
173			`RESET_VALUE`
174			`16'h0000`
175
176
177
178			`fs-sim`
179
180
181
182	131	jt_eaton
183
184	135	jt_eaton
185	131	jt_eaton
186	135	jt_eaton
187			`rtl`
188			`verilog:Kactus2:`
189			`verilog`
190
191	131	jt_eaton
192	135	jt_eaton
193
194			`verilog`
195
196
197			`ipxact:library="Testbench"`
198			`ipxact:name="toolflow"`
199			`ipxact:version="verilog"/>`
200
201
202	131	jt_eaton
203
204
205	135	jt_eaton
206			`common:common:`
207			`Verilog`
208
209
210			`fs-common`
211
212
213	131	jt_eaton
214
215
216
217	135	jt_eaton
218			`sim:Simulation:`
219			`Verilog`
220
221
222			`fs-sim`
223
224
225	131	jt_eaton
226	135	jt_eaton
227			`syn:Synthesis:`
228			`Verilog`
229
230
231			`fs-syn`
232
233
234	131	jt_eaton
235
236	134	jt_eaton
237	135	jt_eaton
238			`doc`
239
240
241			`ipxact:library="Testbench"`
242			`ipxact:name="toolflow"`
243			`ipxact:version="documentation"/>`
244
245			`:Documentation:`
246			`Verilog`
247
248	134	jt_eaton
249
250
251
252	135	jt_eaton
253	134	jt_eaton
254
255
256
257
258
259
260
261	135	jt_eaton
262			`BITS16`
263			`RESET_VALUE'h0`
264
265	134	jt_eaton
266	135	jt_eaton
267	134	jt_eaton
268
269
270
271	135	jt_eaton	`capture_value`
272			`wire`
273			`in`
274			`BITS-10`
275
276	134	jt_eaton
277
278	135	jt_eaton	`update_value`
279			`reg`
280			`out`
281			`BITS-10`
282
283	134	jt_eaton
284
285
286	135	jt_eaton	`test_logic_reset`
287			`wire`
288			`in`
289
290
291	134	jt_eaton
292
293
294	135	jt_eaton	`capture_dr`
295			`wire`
296			`in`
297
298
299	134	jt_eaton
300
301
302	135	jt_eaton	`shift_dr`
303			`wire`
304			`in`
305
306
307	134	jt_eaton
308
309
310	135	jt_eaton	`shiftcapture_dr_clk`
311			`wire`
312			`in`
313
314
315	134	jt_eaton
316
317
318
319	135	jt_eaton	`update_dr_clk`
320			`wire`
321			`in`
322
323
324	134	jt_eaton
325
326	135	jt_eaton	`tdi`
327			`wire`
328			`in`
329
330
331	131	jt_eaton
332	135	jt_eaton	`tdo`
333			`wire`
334			`out`
335
336
337	131	jt_eaton
338	135	jt_eaton	`select`
339			`wire`
340			`in`
341
342
343	131	jt_eaton
344
345
346
347
348	135	jt_eaton
349	131	jt_eaton
350	135	jt_eaton
351	131	jt_eaton
352
353
354
355
356	135	jt_eaton
357	131	jt_eaton
358
359	135	jt_eaton
360			`fs-common`
361	131	jt_eaton
362	135	jt_eaton
363
364			`../verilog/classic_rpc_reg`
365			`verilogSourcefragment`
366
367	131	jt_eaton
368
369	135	jt_eaton
370
371			`../verilog/copyright`
372			`verilogSourceinclude`
373
374	131	jt_eaton
375
376
377	135	jt_eaton
378	131	jt_eaton
379	135	jt_eaton
380			`fs-sim`
381	134	jt_eaton
382	135	jt_eaton
383
384
385			`../verilog/common/jtag_classic_rpc_reg`
386			`verilogSourcemodule`
387
388	134	jt_eaton
389
390	135	jt_eaton
391			`dest_dir`
392			`../views/sim/`
393			`verilogSourcelibraryDir`
394
395	134	jt_eaton
396	135	jt_eaton
397	134	jt_eaton
398	135	jt_eaton
399
400			`fs-syn`
401
402
403
404			`../verilog/common/jtag_classic_rpc_reg`
405			`verilogSourcemodule`
406
407
408
409
410			`dest_dir`
411			`../views/syn/`
412			`verilogSourcelibraryDir`
413
414
415
416
417
418
419
420
421
422			`fs-lint`
423
424
425
426			`../verilog/common/jtag_classic_rpc_reg`
427			`verilogSourcemodule`
428
429
430
431
432
433			`dest_dir../views/syn/`
434			`verilogSourcelibraryDir`
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453