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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_in_reg.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
rpc_in_reg  default
 
 
 
 
 

 
 
 jtag
  
  
    
 
 
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
 
 
 
    
 
 

 
 
 
 
 
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      jtag_rpc_in_reg
    
  

 
 
 
 
 
 
 

 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
 
 
 
   
      fs-common
 
      
        
        ../verilog/jtag_rpc_in_reg
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
 
 
   
      fs-sim
 
      
        
        ../verilog/common/jtag_rpc_in_reg
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
 
      
        
        ../verilog/common/jtag_rpc_in_reg
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 

 
 
 
 
 

BITS16
RESET_VALUE'h0

 

 
 
 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
 
 
 
 
 
capture_value
wire
in
BITS-10

 
 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_in_reg.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`rpc_in_reg default`
16
17
18
19
20
21	134	jt_eaton
22	131	jt_eaton
23
24	134	jt_eaton	`jtag`
25
26
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28	131	jt_eaton
29
30
31	134	jt_eaton
32			`capture_dr`
33			`capture_dr`
34
35	131	jt_eaton
36	134	jt_eaton
37			`shift_dr`
38			`shift_dr`
39
40	131	jt_eaton
41
42	134	jt_eaton
43			`tdi`
44			`tdi`
45
46	131	jt_eaton
47	134	jt_eaton
48			`tdo`
49			`tdo`
50
51	131	jt_eaton
52	134	jt_eaton
53			`select`
54			`select`
55
56	131	jt_eaton
57
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61	134	jt_eaton
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63	131	jt_eaton
64	134	jt_eaton
65	131	jt_eaton
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76	134	jt_eaton
77	131	jt_eaton
78	134	jt_eaton
79
80
81			`gen_verilog`
82			`104.0`
83			`none`
84			`common`
85			`./tools/verilog/gen_verilog`
86
87
88			`destination`
89			`jtag_rpc_in_reg`
90
91
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106	131	jt_eaton
107
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110	134	jt_eaton
111			`verilog`
112
113
114			`spirit:library="Testbench"`
115			`spirit:name="toolflow"`
116			`spirit:version="verilog"/>`
117
118
119	131	jt_eaton
120	134	jt_eaton
121
122	131	jt_eaton
123	134	jt_eaton	`commoncommon`
124			`Verilog`
125
126
127			`fs-common`
128
129
130
131
132
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134
135
136	131	jt_eaton	`sim:Simulation:`
137			`Verilog`
138
139
140			`fs-sim`
141
142
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145			`syn:Synthesis:`
146			`Verilog`
147
148
149			`fs-syn`
150
151
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153
154
155
156
157
158			`doc`
159
160
161			`spirit:library="Testbench"`
162			`spirit:name="toolflow"`
163			`spirit:version="documentation"/>`
164
165			`:Documentation:`
166			`Verilog`
167
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174
175	134	jt_eaton
176
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184			`fs-common`
185
186
187
188			`../verilog/jtag_rpc_in_reg`
189			`verilogSourcefragment`
190
191
192
193
194
195			`../verilog/copyright`
196			`verilogSourceinclude`
197
198
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204
205
206
207			`fs-sim`
208
209
210
211			`../verilog/common/jtag_rpc_in_reg`
212			`verilogSourcemodule`
213
214
215
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217			`dest_dir`
218			`../views/sim/`
219			`verilogSourcelibraryDir`
220
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225
226			`fs-syn`
227
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230
231
232			`../verilog/common/jtag_rpc_in_reg`
233			`verilogSourcemodule`
234
235
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237
238
239			`dest_dir`
240			`../views/syn/`
241			`verilogSourcelibraryDir`
242
243
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245
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247
248
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250
251
252			`fs-lint`
253
254			`dest_dir../views/syn/`
255			`verilogSourcelibraryDir`
256
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268	131	jt_eaton
269			`BITS16`
270			`RESET_VALUE'h0`
271
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275	134	jt_eaton
276
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279	131	jt_eaton	`clk`
280			`wire`
281			`in`
282
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284	134	jt_eaton
285	131	jt_eaton	`reset`
286			`wire`
287			`in`
288
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294
295
296			`capture_value`
297			`wire`
298			`in`
299			`BITS-10`
300
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307	134	jt_eaton
308	131	jt_eaton
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