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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_reg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
rpc_reg  default
 
 

 
 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 

       
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

BITS16
RESET_VALUE'h0

 

 
clk
wire
in

 
reset
wire
in

 
 
tdi
wire
in

 
select
wire
in

 
update_dr
wire
in

 
capture_dr
wire
in

 
shift_dr
wire
in

 
 
tdo
wire
out

 
 
capture_value
wire
in
BITS-10

 
 
update_value
wire
out
BITS-10

 
 
 
 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_reg.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
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6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`rpc_reg default`
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33			`fs-sim`
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37			`dest_dir`
38			`../verilog/`
39			`verilogSourcelibraryDir`
40
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46			`fs-syn`
47
48
49			`dest_dir`
50			`../verilog/`
51			`verilogSourcelibraryDir`
52
53
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61			`fs-lint`
62
63			`dest_dir../verilog/`
64			`verilogSourcelibraryDir`
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86			`sim:Simulation:`
87			`Verilog`
88
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90			`fs-sim`
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95			`syn:Synthesis:`
96			`Verilog`
97
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99			`fs-syn`
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106			`doc`
107
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109			`spirit:library="Testbench"`
110			`spirit:name="toolflow"`
111			`spirit:version="documentation"/>`
112
113			`:Documentation:`
114			`Verilog`
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127			`BITS16`
128			`RESET_VALUE'h0`
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133			`clk`
134			`wire`
135			`in`
136
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138			`reset`
139			`wire`
140			`in`
141
142
143
144			`tdi`
145			`wire`
146			`in`
147
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149			`select`
150			`wire`
151			`in`
152
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154			`update_dr`
155			`wire`
156			`in`
157
158
159			`capture_dr`
160			`wire`
161			`in`
162
163
164			`shift_dr`
165			`wire`
166			`in`
167
168
169
170			`tdo`
171			`wire`
172			`out`
173
174
175
176			`capture_value`
177			`wire`
178			`in`
179			`BITS-10`
180
181
182
183			`update_value`
184			`wire`
185			`out`
186			`BITS-10`
187
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