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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
sync  default
 
 

 
 
 jtag
  
  
    
 
      
        clk
        jtag_clk
      
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr
        update_dr
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
 
 
    
 
 
 
 syn_jtag
  
  
    
 
 
 
      
        clk
        syn_clk
      
 
      
        capture_dr
        syn_capture_dr
      
 
      
        shift_dr
        syn_shift_dr
      
 
      
        update_dr
        syn_update_dr
      
 
 
      
        tdi
        syn_tdi
      
 
      
        tdo
        syn_tdo
      
 
      
        select
        syn_select
      
 
 
 
    
 
 

 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`sync default`
16
17
18
19
20
21			`jtag`
22
23
24
25
26
27			`clk`
28			`jtag_clk`
29
30
31
32			`test_logic_reset`
33			`test_logic_reset`
34
35
36
37			`capture_dr`
38			`capture_dr`
39
40
41
42			`shift_dr`
43			`shift_dr`
44
45
46
47			`update_dr`
48			`update_dr`
49
50
51
52
53			`tdi`
54			`tdi`
55
56
57
58			`tdo`
59			`tdo`
60
61
62
63			`select`
64			`select`
65
66
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71
72
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74			`syn_jtag`
75
76
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81
82			`clk`
83			`syn_clk`
84
85
86
87			`capture_dr`
88			`syn_capture_dr`
89
90
91
92			`shift_dr`
93			`syn_shift_dr`
94
95
96
97			`update_dr`
98			`syn_update_dr`
99
100
101
102
103			`tdi`
104			`syn_tdi`
105
106
107
108			`tdo`
109			`syn_tdo`
110
111
112
113			`select`
114			`syn_select`
115
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132
133			`sim:Simulation:`
134			`Verilog`
135
136
137			`fs-sim`
138
139
140
141
142			`syn:Synthesis:`
143			`Verilog`
144
145
146			`fs-syn`
147
148
149
150
151
152
153			`doc`
154
155
156			`spirit:library="Testbench"`
157			`spirit:name="toolflow"`
158			`spirit:version="documentation"/>`
159
160			`:Documentation:`
161			`Verilog`
162
163
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172
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174	133	jt_eaton
175	131	jt_eaton
176
177			`clk`
178			`wire`
179			`in`
180
181
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195
196
197			`fs-sim`
198
199
200
201			`dest_dir`
202			`../verilog/`
203			`verilogSource`
204			`libraryDir`
205
206
207
208
209
210
211			`fs-syn`
212
213
214			`dest_dir`
215			`../verilog/`
216			`verilogSource`
217			`libraryDir`
218
219
220
221
222
223
224
225
226
227			`fs-lint`
228
229			`dest_dir`
230			`../verilog/`
231			`verilogSource`
232			`libraryDir`
233
234
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