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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
sync  default
 
 

 
 
 jtag
  
  
    
 
      
        clk
        jtag_clk
      
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr
        update_dr
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
 
 
    
 
 
 
 syn_jtag
  
  
    
 
 
 
      
        clk
        syn_clk
      
 
      
        capture_dr
        syn_capture_dr
      
 
      
        shift_dr
        syn_shift_dr
      
 
      
        update_dr
        syn_update_dr
      
 
 
      
        tdi
        syn_tdi
      
 
      
        tdo
        syn_tdo
      
 
      
        select
        syn_select
      
 
 
 
    
 
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      jtag_sync
    
  

 
 
 
 

 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-sim
 
     
        
        ../verilog/sync
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
  
 
 
 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`sync default`
16
17
18
19
20
21			`jtag`
22
23
24
25
26
27			`clk`
28			`jtag_clk`
29
30
31
32			`test_logic_reset`
33			`test_logic_reset`
34
35
36
37			`capture_dr`
38			`capture_dr`
39
40
41
42			`shift_dr`
43			`shift_dr`
44
45
46
47			`update_dr`
48			`update_dr`
49
50
51
52
53			`tdi`
54			`tdi`
55
56
57
58			`tdo`
59			`tdo`
60
61
62
63			`select`
64			`select`
65
66
67
68
69
70
71
72
73
74			`syn_jtag`
75
76
77
78
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80
81
82			`clk`
83			`syn_clk`
84
85
86
87			`capture_dr`
88			`syn_capture_dr`
89
90
91
92			`shift_dr`
93			`syn_shift_dr`
94
95
96
97			`update_dr`
98			`syn_update_dr`
99
100
101
102
103			`tdi`
104			`syn_tdi`
105
106
107
108			`tdo`
109			`syn_tdo`
110
111
112
113			`select`
114			`syn_select`
115
116
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119
120
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123
124
125	134	jt_eaton
126	131	jt_eaton
127
128
129	134	jt_eaton
130
131			`gen_verilog`
132			`104.0`
133			`none`
134			`common`
135			`./tools/verilog/gen_verilog`
136
137
138			`destination`
139			`jtag_sync`
140
141
142
143
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150
151
152	131	jt_eaton
153
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157	134	jt_eaton	`verilog`
158
159
160			`spirit:library="Testbench"`
161			`spirit:name="toolflow"`
162			`spirit:version="verilog"/>`
163
164
165
166
167
168
169
170			`commoncommon`
171			`Verilog`
172
173
174			`fs-common`
175
176
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180
181
182	131	jt_eaton	`sim:Simulation:`
183			`Verilog`
184
185
186			`fs-sim`
187
188
189
190
191			`syn:Synthesis:`
192			`Verilog`
193
194
195			`fs-syn`
196
197
198
199
200
201
202			`doc`
203
204
205			`spirit:library="Testbench"`
206			`spirit:name="toolflow"`
207			`spirit:version="documentation"/>`
208
209			`:Documentation:`
210			`Verilog`
211
212
213
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221
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223	133	jt_eaton
224	131	jt_eaton
225
226			`clk`
227			`wire`
228			`in`
229
230
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233
234
235
236
237
238
239
240
241
242
243
244
245
246			`fs-sim`
247
248	134	jt_eaton
249
250			`../verilog/sync`
251			`verilogSourcefragment`
252
253
254
255
256
257			`../verilog/copyright`
258			`verilogSourceinclude`
259
260
261
262	131	jt_eaton
263	134	jt_eaton
264
265
266
267
268			`fs-sim`
269
270
271	131	jt_eaton
272			`dest_dir`
273			`../verilog/`
274			`verilogSource`
275			`libraryDir`
276
277
278
279
280
281
282			`fs-syn`
283
284
285			`dest_dir`
286			`../verilog/`
287			`verilogSource`
288			`libraryDir`
289
290
291
292
293
294
295
296
297
298			`fs-lint`
299
300			`dest_dir`
301			`../verilog/`
302			`verilogSource`
303			`libraryDir`
304
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