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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
tap  default
 
 
 
 
 

 
 jtag
  
  
    
 
      
        test_logic_reset
        test_logic_reset_o
        reg
        
      
 
      
        capture_dr
        
        capture_dr_o
        reg
        
      
 
      
        shift_dr
        
        shift_dr_o
        reg
        
      
 
      
        update_dr_clk
        update_dr_clk_o
        wire
       
      
 
      
        tdi
        tdi_o
       wire
      
      
 
      
      tdo
      
      tdo_i
      
      
      
 
      
      select
      
      select_o
      
      
      
 
      
      shiftcapture_dr_clk
      
      shiftcapture_dr_clk_o
      
      
      
 
    
 
 
 
 aux_jtag
  
  
    
 
      
        test_logic_reset
        aux_test_logic_reset_o
        wire
        
      
 
      
        capture_dr
        
        aux_capture_dr_o
        wire
        
      
 
      
        shift_dr
        
        aux_shift_dr_o
        wire
        
      
 
      
        update_dr_clk
        aux_update_dr_clk_o
        wire
       
      
 
      
        tdi
        aux_tdi_o
       wire
      
      
 
      
      tdo
      
      aux_tdo_i
      
      
      
 
      
      select
      
      aux_select_o
      
      
      
 
      
      shiftcapture_dr_clk
      
      aux_shiftcapture_dr_clk_o
      
      
      
 
    
 
 
 
 
 
 tclk_pad
  
  
  
    
      
        pad_in
        tclk_pad_in
      
 
    
 
 
 
 tdi_pad
  
  
  
    
      
        pad_in
        tdi_pad_in
      
 
    
 
 
 
 tms_pad
  
  
  
    
      
        pad_in
        tms_pad_in
      
 
    
 
 
 
 trst_n_pad
  
  
  
    
      
        pad_in
        trst_n_pad_in
      
 
    
 
 
 
 
 
 tdo_pad
  
  
  
    
      
        pad_out
        tdo_pad_out
      
      
        pad_oe
        tdo_pad_oe
      
 
    
 
 
 

 
 
 
 
 
 
 
 
 
 

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../verilog
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../verilog
    
    
      view
      syn
    
  

 
 
 

 
 
 
 
 
 
 
 
 
 
 

       
 
              
              Hierarchical
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="def.design"/>
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 

INST_LENGTH4
INST_RETURN4'b1101
INST_RESET4'b1111
CHIP_ID_VAL32'h12345678
NUM_USER2
EXTEST4'b0000
USER8'b1010_1001
SAMPLE4'b0001
HIGHZ_MODE4'b0010
CHIP_ID_ACCESS4'b0011
CLAMP4'b1000
RPC_DATA4'b1010
RPC_ADD4'b1001
BYPASS4'b1111
 
 

 
 

 
 
 
 
tap_highz_mode
reg
out

 
bsr_output_mode
reg
out

 
bsr_tdo_i
wire
in

 
jtag_clk
wire
out

 
update_dr_o
reg
out

 
bsr_select_o
wire
out

 

 

 
 
 
 
 

 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/jtag_tap
        verilogSourcemodule
      
 
      
        dest_dir
        ../verilog/sim/
        verilogSourcelibraryDir
      
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/SYNTHESYS
        verilogSourceinclude
      
 
 
 
 
      
        
        ../verilog/jtag_tap
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`tap default`
16
17
18
19
20
21
22
23			`jtag`
24
25
26
27
28
29			`test_logic_reset`
30			`test_logic_reset_o`
31			`reg`
32
33
34
35
36			`capture_dr`
37
38			`capture_dr_o`
39			`reg`
40
41
42
43
44			`shift_dr`
45
46			`shift_dr_o`
47			`reg`
48
49
50
51
52			`update_dr_clk`
53			`update_dr_clk_o`
54			`wire`
55
56
57
58
59			`tdi`
60			`tdi_o`
61			`wire`
62
63
64
65
66			`tdo`
67
68			`tdo_i`
69	133	jt_eaton
70	131	jt_eaton
71
72
73
74			`select`
75
76			`select_o`
77	133	jt_eaton
78	131	jt_eaton
79
80
81
82			`shiftcapture_dr_clk`
83
84			`shiftcapture_dr_clk_o`
85
86
87
88
89
90
91
92
93	133	jt_eaton	`aux_jtag`
94
95
96
97	131	jt_eaton
98	133	jt_eaton
99			`test_logic_reset`
100			`aux_test_logic_reset_o`
101			`wire`
102
103
104	131	jt_eaton
105	133	jt_eaton
106			`capture_dr`
107
108			`aux_capture_dr_o`
109			`wire`
110
111
112
113
114			`shift_dr`
115
116			`aux_shift_dr_o`
117			`wire`
118
119
120
121
122			`update_dr_clk`
123			`aux_update_dr_clk_o`
124			`wire`
125
126
127
128
129			`tdi`
130			`aux_tdi_o`
131			`wire`
132
133
134
135
136			`tdo`
137
138			`aux_tdo_i`
139
140
141
142
143
144			`select`
145
146			`aux_select_o`
147
148
149
150
151
152			`shiftcapture_dr_clk`
153
154			`aux_shiftcapture_dr_clk_o`
155
156
157
158
159
160
161
162
163
164
165	131	jt_eaton	`tclk_pad`
166
167
168
169
170
171			`pad_in`
172			`tclk_pad_in`
173
174
175
176
177
178
179			`tdi_pad`
180
181
182
183
184
185			`pad_in`
186			`tdi_pad_in`
187
188
189
190
191
192
193			`tms_pad`
194
195
196
197
198
199			`pad_in`
200			`tms_pad_in`
201
202
203
204
205
206
207			`trst_n_pad`
208
209
210
211
212
213			`pad_in`
214			`trst_n_pad_in`
215
216
217
218
219
220
221
222
223			`tdo_pad`
224
225
226
227
228
229			`pad_out`
230			`tdo_pad_out`
231
232
233			`pad_oe`
234			`tdo_pad_oe`
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258			`gen_verilogLib_sim`
259			`105.0`
260			`none`
261			`:Simulation:`
262			`./tools/verilog/gen_verilogLib`
263
264
265			`dest_dir`
266			`../verilog`
267
268
269			`view`
270			`sim`
271
272
273
274
275
276
277			`gen_verilogLib_syn`
278			`105.0`
279			`none`
280			`:Synthesis:`
281			`./tools/verilog/gen_verilogLib`
282
283
284			`dest_dir`
285			`../verilog`
286
287
288			`view`
289			`syn`
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312			`Hierarchical`
313
314			`spirit:library="cde"`
315			`spirit:name="jtag"`
316			`spirit:version="def.design"/>`
317
318
319
320
321			`sim:Simulation:`
322			`Verilog`
323
324
325			`fs-sim`
326
327
328
329
330			`syn:Synthesis:`
331			`Verilog`
332
333
334			`fs-syn`
335
336
337
338
339
340
341
342
343			`doc`
344
345
346			`spirit:library="Testbench"`
347			`spirit:name="toolflow"`
348			`spirit:version="documentation"/>`
349
350			`:Documentation:`
351			`Verilog`
352
353
354
355
356
357
358
359
360
361
362
363			`INST_LENGTH4`
364			`INST_RETURN4'b1101`
365			`INST_RESET4'b1111`
366			`CHIP_ID_VAL32'h12345678`
367			`NUM_USER2`
368			`EXTEST4'b0000`
369			`USER8'b1010_1001`
370			`SAMPLE4'b0001`
371			`HIGHZ_MODE4'b0010`
372			`CHIP_ID_ACCESS4'b0011`
373			`CLAMP4'b1000`
374			`RPC_DATA4'b1010`
375			`RPC_ADD4'b1001`
376			`BYPASS4'b1111`
377
378
379
380
381
382
383
384
385
386
387			`tap_highz_mode`
388			`reg`
389			`out`
390
391
392			`bsr_output_mode`
393			`reg`
394			`out`
395
396
397			`bsr_tdo_i`
398			`wire`
399			`in`
400
401
402			`jtag_clk`
403			`wire`
404			`out`
405
406
407			`update_dr_o`
408			`reg`
409			`out`
410
411
412			`bsr_select_o`
413			`wire`
414			`out`
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431			`fs-sim`
432
433
434
435
436			`../verilog/jtag_tap`
437			`verilogSourcemodule`
438
439
440
441			`dest_dir`
442			`../verilog/sim/`
443			`verilogSourcelibraryDir`
444
445
446
447
448
449
450			`fs-syn`
451
452
453
454			`../verilog/SYNTHESYS`
455			`verilogSourceinclude`
456
457
458
459
460
461
462
463			`../verilog/jtag_tap`
464			`verilogSourcemodule`
465
466
467
468
469			`dest_dir`
470			`../verilog/syn/`
471			`verilogSourcelibraryDir`
472
473
474
475
476
477
478
479
480			`fs-lint`
481
482			`dest_dir`
483			`../verilog/syn/`
484			`verilogSourcelibraryDir`
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503