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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [icarus/] [alt_1/] [test_define] - Blame information for rev 131

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1 131 jt_eaton
 
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reg actual;
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parameter       EXTEST=4'b0000;
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parameter       SAMPLE=4'b0001;
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parameter       HIGHZ_MODE=4'b0010;
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parameter       CHIP_ID_ACCESS=4'b0011;
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parameter       CLAMP=4'b1000;
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parameter       RPC_DATA=4'b1010;
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parameter       RPC_ADD=4'b1001;
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parameter       BYPASS=4'b1111;
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parameter       INST_RETURN=4'b1101;
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initial
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begin
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$display("              ");
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$display("              ===================================================");
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$display("              Test Start");
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$display("              ===================================================");
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$display("              ");
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test.cg.next(2);
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test.jtag_model.enable_tclk;
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test.cg.next(20);
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test.cg.next(20);
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test.jtag_model.enable_trst_n;
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test.jtag_model.enable_reset;
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test.jtag_model.init;
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test.cg.next(10);
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test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
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                Shift_Cmp_64(64'h1248124812481248,64'h0000000000000000   );
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test.cg.next(100);
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test.jtag_model.LoadTapInst(SAMPLE,INST_RETURN);
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                Shift_Cmp_64(64'h0000000000000000,64'h0000000000000000);
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test.cg.next(100);
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test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
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                Shift_Cmp_64(64'h0800000002100010,64'h1000000004200020);
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test.cg.next(100);
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test.cg.exit;
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end
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task automatic  Shift_Cmp_64;    // Initialize boundary register with outputs disabled
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                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
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  parameter [15:0] LENGTH =  64;
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  input [LENGTH:1]  Dataout;
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  input [LENGTH:1]  DataExp;
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  integer i;
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  reg [LENGTH:1]  DataBack;
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  begin
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    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
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    for (i = 1; i <= LENGTH; i = i+1)
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       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
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    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
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   if (DataBack  !== DataExp )
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   begin
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   test.cg.fail  (" Shift_cmp  receive error  ");
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   end
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    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
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  end
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endtask // ShiftRegister
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