URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [icarus/] [classic/] [test_define] - Blame information for rev 131

Details | Compare with Previous | View Log


reg actual;
 
 
parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;
 
initial
begin
$display("              ");
$display("              ===================================================");
$display("              Test Start");
$display("              ===================================================");
$display("              ");
test.cg.next(2);
test.jtag_model.enable_tclk;
test.cg.next(20);
 
test.cg.next(20);
test.jtag_model.enable_trst_n;
test.jtag_model.enable_reset;
test.jtag_model.init;
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
                Shift_Cmp_8(8'h00,8'h12);
                Shift_Cmp_8(8'h34,8'h00);
                Shift_Cmp_8(8'h12,8'h34);
                Shift_Cmp_8(8'hff,8'h12);
                Shift_Cmp_8(8'hcd,8'hff);
 
test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_DATA,INST_RETURN);
                Shift_Cmp_24(24'ha5a5a5,24'h123456);
 
test.cg.next(100);
 
test.rpc_2_reg  <= 24'h654321;
test.jtag_model.LoadTapInst(RPC_DATA,INST_RETURN);
                Shift_Cmp_24(24'ha5a5a5,24'h654321);
 
 
 
test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
 
 
                Shift_Cmp_24(24'h124708,24'h248e10);
 
test.cg.next(100);
 
 
test.cg.exit;
end
 
 
 
 
 
 
task automatic  Shift_Cmp_8;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  8;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_24;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  24;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg actual;`
2
3
4			`parameter EXTEST=4'b0000;`
5			`parameter SAMPLE=4'b0001;`
6			`parameter HIGHZ_MODE=4'b0010;`
7			`parameter CHIP_ID_ACCESS=4'b0011;`
8			`parameter CLAMP=4'b1000;`
9			`parameter RPC_DATA=4'b1010;`
10			`parameter RPC_ADD=4'b1001;`
11			`parameter BYPASS=4'b1111;`
12			`parameter INST_RETURN=4'b1101;`
13
14			`initial`
15			`begin`
16			`$display(" ");`
17			`$display(" ===================================================");`
18			`$display(" Test Start");`
19			`$display(" ===================================================");`
20			`$display(" ");`
21			`test.cg.next(2);`
22			`test.jtag_model.enable_tclk;`
23			`test.cg.next(20);`
24
25			`test.cg.next(20);`
26			`test.jtag_model.enable_trst_n;`
27			`test.jtag_model.enable_reset;`
28			`test.jtag_model.init;`
29			`test.cg.next(10);`
30			`test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);`
31			`test.cg.next(100);`
32			`test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);`
33
34
35			`test.cg.next(100);`
36			`test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);`
37			`test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);`
38
39
40			`test.cg.next(100);`
41			`test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);`
42			`Shift_Cmp_8(8'h00,8'h12);`
43			`Shift_Cmp_8(8'h34,8'h00);`
44			`Shift_Cmp_8(8'h12,8'h34);`
45			`Shift_Cmp_8(8'hff,8'h12);`
46			`Shift_Cmp_8(8'hcd,8'hff);`
47
48			`test.cg.next(100);`
49			`test.jtag_model.LoadTapInst(RPC_DATA,INST_RETURN);`
50			`Shift_Cmp_24(24'ha5a5a5,24'h123456);`
51
52			`test.cg.next(100);`
53
54			`test.rpc_2_reg <= 24'h654321;`
55			`test.jtag_model.LoadTapInst(RPC_DATA,INST_RETURN);`
56			`Shift_Cmp_24(24'ha5a5a5,24'h654321);`
57
58
59
60			`test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);`
61
62
63			`Shift_Cmp_24(24'h124708,24'h248e10);`
64
65			`test.cg.next(100);`
66
67
68			`test.cg.exit;`
69			`end`
70
71
72
73
74
75
76			`task automatic Shift_Cmp_8; // Initialize boundary register with outputs disabled`
77			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
78
79			`parameter [15:0] LENGTH = 8;`
80
81
82			`input [LENGTH:1] Dataout;`
83			`input [LENGTH:1] DataExp;`
84
85			`integer i;`
86
87			`reg [LENGTH:1] DataBack;`
88
89			`begin`
90			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
91			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
92			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
93			`for (i = 1; i <= LENGTH; i = i+1)`
94			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
95			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
96
97			`if (DataBack !== DataExp )`
98			`begin`
99			`test.cg.fail (" Shift_cmp receive error ");`
100			`end`
101
102			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
103			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
104			`end`
105			`endtask // ShiftRegister`
106
107
108
109
110			`task automatic Shift_Cmp_24; // Initialize boundary register with outputs disabled`
111			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
112
113			`parameter [15:0] LENGTH = 24;`
114
115
116			`input [LENGTH:1] Dataout;`
117			`input [LENGTH:1] DataExp;`
118
119			`integer i;`
120
121			`reg [LENGTH:1] DataBack;`
122
123			`begin`
124			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
125			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
126			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
127			`for (i = 1; i <= LENGTH; i = i+1)`
128			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
129			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
130
131			`if (DataBack !== DataExp )`
132			`begin`
133			`test.cg.fail (" Shift_cmp receive error ");`
134			`end`
135
136			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
137			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
138			`end`
139			`endtask // ShiftRegister`
140
141
142
143
144
145
146

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [icarus/] [classic/] [test_define] - Blame information for rev 131