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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [verilog/] [tb.rpc_2] - Blame information for rev 131

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reg [JTAG_USER2_WIDTH-1:0] rpc_2_reg;
 
always @(posedge clk or posedge reset)
begin
if(reset)  rpc_2_reg <= JTAG_USER2_RESET;
else       rpc_2_reg <= rpc_2_reg;
end
 
assign  rpc_2_wire =   rpc_2_reg;

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`reg [JTAG_USER2_WIDTH-1:0] rpc_2_reg;`
4
5			`always @(posedge clk or posedge reset)`
6			`begin`
7			`if(reset) rpc_2_reg <= JTAG_USER2_RESET;`
8			`else rpc_2_reg <= rpc_2_reg;`
9			`end`
10
11			`assign rpc_2_wire = rpc_2_reg;`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [verilog/] [tb.rpc_2] - Blame information for rev 131