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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_classic_sync_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
classic_sync_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      jtag_classic_sync_tb
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_SEL8
    JTAG_USER1_WIDTH8
    JTAG_USER1_RESET8'h12
    JTAG_USER2_WIDTH24
    JTAG_USER2_RESET24'h123456
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="tap_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="classic_sync_bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
   
      fs-common
 
 
 
 
 
      
        
        ../verilog/tb.rpc_2
        verilogSource
        fragment
      
 
 
   
 
 
   
      fs-sim
 
 
 
 
 
      
        
        ../verilog/common/jtag_classic_sync_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/jtag_classic_sync_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`classic_sync_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	134	jt_eaton	`jtag_classic_sync_tb`
34	131	jt_eaton
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50			`JTAG_SEL8`
51			`JTAG_USER1_WIDTH8`
52			`JTAG_USER1_RESET8'h12`
53			`JTAG_USER2_WIDTH24`
54			`JTAG_USER2_RESET24'h123456`
55			`JTAG_MODEL_DIVCNT 4'h4`
56			`JTAG_MODEL_SIZE 4`
57
58
59
60
61
62			`Params`
63
64
65			`spirit:library="cde"`
66			`spirit:name="jtag"`
67			`spirit:version="tap_dut.params"/>`
68
69
70
71
72
73			`Bfm`
74
75			`spirit:library="cde"`
76			`spirit:name="jtag"`
77			`spirit:version="classic_sync_bfm.design"/>`
78
79
80
81
82			`icarus`
83
84
85			`spirit:library="Testbench"`
86			`spirit:name="toolflow"`
87			`spirit:version="icarus"/>`
88
89
90
91
92
93
94
95			`commoncommon`
96			`Verilog`
97
98
99			`fs-common`
100
101
102
103
104
105			`sim:Simulation:`
106			`Verilog`
107
108
109			`fs-sim`
110
111
112
113
114			`lint:Lint:`
115			`Verilog`
116
117
118			`fs-lint`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137			`fs-common`
138
139
140
141
142
143
144
145			`../verilog/tb.rpc_2`
146			`verilogSource`
147			`fragment`
148
149
150
151
152
153
154
155			`fs-sim`
156
157
158
159
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161
162
163	134	jt_eaton	`../verilog/common/jtag_classic_sync_tb`
164	131	jt_eaton	`verilogSourcemodule`
165
166
167
168
169
170
171
172			`fs-lint`
173
174
175	134	jt_eaton	`../verilog/common/jtag_classic_sync_tb`
176	131	jt_eaton	`verilogSourcemodule`
177
178
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_classic_sync_tb.xml] - Blame information for rev 134