URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_tap_lint.xml] - Blame information for rev 133

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
tap_lint
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  103.0
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 
 

 
 
       
 
              
              Dut
              
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="tap_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
 
      
 
 
 

 
 
 
 
 
 
 
 

 
 
 
   
      fs-lint
      
        
        ../verilog/lint/jtag_tap_lint
        verilogSource
        module
      
 
 
 
   
 
 
 

 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`tap_lint`
16
17
18
19	133	jt_eaton
20	131	jt_eaton
21	133	jt_eaton
22			`elab_verilog`
23			`103.0`
24			`none`
25			`:Simulation:`
26			`>`
27			`./tools/verilog/elab_verilog`
28
29
30			`configuration`
31			`default`
32
33
34			`dest_dir`
35			`io_ports`
36
37
38
39	131	jt_eaton
40	133	jt_eaton
41			`gen_design`
42			`103.0`
43			`none`
44			`:Simulation:`
45			`>`
46			`./tools/verilog/gen_design`
47
48
49			`dest_dir`
50			`io_ports`
51
52
53
54	131	jt_eaton
55	133	jt_eaton
56	131	jt_eaton
57	133	jt_eaton
58
59
60
61	131	jt_eaton
62
63
64
65
66
67			`Dut`
68
69
70			`spirit:library="cde"`
71			`spirit:name="jtag"`
72			`spirit:version="tap_dut.params"/>`
73
74
75
76
77
78			`lint`
79			`:Lint:`
80			`Verilog`
81			`fs-lint`
82
83
84
85
86
87			`rtl_check`
88
89
90			`spirit:library="Testbench"`
91			`spirit:name="toolflow"`
92			`spirit:version="rtl_check"/>`
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115			`fs-lint`
116
117
118			`../verilog/lint/jtag_tap_lint`
119			`verilogSource`
120			`module`
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_tap_lint.xml] - Blame information for rev 133