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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_tap_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
tap_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_SEL2
    JTAG_USER1_WIDTH8
    JTAG_USER1_RESET8'h12
    JTAG_USER2_WIDTH24
    JTAG_USER2_RESET24'h123456
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="tap_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
   
      fs-common
 
 
 
 
 
      
        
        ../verilog/tb.rpc_2
        verilogSource
        fragment
      
 
 
   
 
 
   
      fs-sim
 
 
 
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`tap_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33			`top.tb`
34
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57			`JTAG_SEL2`
58			`JTAG_USER1_WIDTH8`
59			`JTAG_USER1_RESET8'h12`
60			`JTAG_USER2_WIDTH24`
61			`JTAG_USER2_RESET24'h123456`
62			`JTAG_MODEL_DIVCNT 4'h4`
63			`JTAG_MODEL_SIZE 4`
64
65
66
67
68
69			`Params`
70
71
72			`spirit:library="cde"`
73			`spirit:name="jtag"`
74			`spirit:version="tap_dut.params"/>`
75
76
77
78
79
80			`Bfm`
81
82			`spirit:library="cde"`
83			`spirit:name="jtag"`
84			`spirit:version="bfm.design"/>`
85
86
87
88
89			`icarus`
90
91
92			`spirit:library="Testbench"`
93			`spirit:name="toolflow"`
94			`spirit:version="icarus"/>`
95
96
97
98
99
100
101
102			`commoncommon`
103			`Verilog`
104
105
106			`fs-common`
107
108
109
110
111
112			`sim:Simulation:`
113			`Verilog`
114
115
116			`fs-sim`
117
118
119
120
121			`lint:Lint:`
122			`Verilog`
123
124
125			`fs-lint`
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`fs-common`
145
146
147
148
149
150
151
152			`../verilog/tb.rpc_2`
153			`verilogSource`
154			`fragment`
155
156
157
158
159
160
161
162			`fs-sim`
163
164
165
166
167
168
169
170			`../verilog/common/top.tb`
171			`verilogSourcemodule`
172
173
174
175
176
177
178
179			`fs-lint`
180
181
182			`../verilog/common/top.tb`
183			`verilogSourcemodule`
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_tap_tb.xml] - Blame information for rev 131