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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [lifo/] [rtl/] [xml/] [cde_lifo_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
lifo
def  default
 
 
 

 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
      dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="cde"
                                   spirit:name="lifo"
                                   spirit:version="def.design"/>
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
       
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

WIDTH8
SIZE2
WORDS4

 

 
clk
wire
in

 
reset
wire
in

 
push
wire
in

 
pop
wire
in

 
 
 
 
din
wire
in
WIDTH-10

 
 
dout
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`lifo`
15			`def default`
16
17
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23
24
25
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29
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31
32
33			`fs-sim`
34
35
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37			`dest_dir`
38			`../verilog/`
39			`verilogSourcelibraryDir`
40
41
42
43
44
45
46			`fs-syn`
47
48
49			`dest_dir`
50			`../verilog/`
51			`verilogSourcelibraryDir`
52
53
54
55
56
57
58
59
60
61			`fs-lint`
62
63			`dest_dir`
64			`../verilog/`
65			`verilogSourcelibraryDir`
66
67
68
69
70
71
72
73
74
75
76
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85			`Hierarchical`
86
87
88			`spirit:library="cde"`
89			`spirit:name="lifo"`
90			`spirit:version="def.design"/>`
91
92
93
94
95
96			`sim:Simulation:`
97
98			`Verilog`
99
100
101			`fs-sim`
102
103
104
105
106			`syn:Synthesis:`
107
108			`Verilog`
109
110
111			`fs-syn`
112
113
114
115
116			`doc`
117
118
119			`spirit:library="Testbench"`
120			`spirit:name="toolflow"`
121			`spirit:version="documentation"/>`
122
123			`:Documentation:`
124			`Verilog`
125
126
127
128
129
130
131
132
133
134
135			`WIDTH8`
136			`SIZE2`
137			`WORDS4`
138
139
140
141
142			`clk`
143			`wire`
144			`in`
145
146
147			`reset`
148			`wire`
149			`in`
150
151
152			`push`
153			`wire`
154			`in`
155
156
157			`pop`
158			`wire`
159			`in`
160
161
162
163
164
165			`din`
166			`wire`
167			`in`
168			`WIDTH-10`
169
170
171
172			`dout`
173			`reg`
174			`out`
175			`WIDTH-10`
176
177
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [lifo/] [rtl/] [xml/] [cde_lifo_def.xml] - Blame information for rev 131