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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [lifo/] [rtl/] [xml/] [cde_lifo_def.xml] - Blame information for rev 133

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1 131 jt_eaton
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
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cde
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lifo
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def  default
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      fs-sim
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        dest_dir
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        ../verilog/
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        verilogSourcelibraryDir
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      fs-syn
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      dest_dir
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        ../verilog/
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        verilogSourcelibraryDir
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      fs-lint
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        dest_dir
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        ../verilog/
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        verilogSourcelibraryDir
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              Hierarchical
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                                   spirit:library="cde"
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                                   spirit:name="lifo"
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                                   spirit:version="def.design"/>
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              sim:*Simulation:*
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              Verilog
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                            fs-sim
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              syn:*Synthesis:*
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              Verilog
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                            fs-syn
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              doc
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                                   spirit:library="Testbench"
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                                   spirit:name="toolflow"
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                                   spirit:version="documentation"/>
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              :*Documentation:*
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              Verilog
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WIDTH8
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SIZE2
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WORDS4
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WRITETHRU0
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DEFAULT8'hff
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clk
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wire
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in
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reset
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wire
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in
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push
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wire
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in
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pop
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wire
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in
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din
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wire
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in
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WIDTH-10
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dout
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reg
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out
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WIDTH-10
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