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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [lifo/] [rtl/] [xml/] [cde_lifo_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
lifo
def  default
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      lifo_def
    
  

 
 
 

 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="cde"
                                   spirit:name="lifo"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
       
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
 
 
 
 
 
   
      fs-common
 
      
        
        ../verilog/lifo_def
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
     
        
        ../verilog/common/lifo_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
      dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 

WIDTH8
SIZE2
WORDS4
WRITETHRU1
 
 

 

 
clk
wire
in

 
reset
wire
in

 
push
wire
in

 
pop
wire
in

 
 
 
 
din
wire
in
WIDTH-10

 
 
dout
wire
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [lifo/] [rtl/] [xml/] [cde_lifo_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`lifo`
15			`def default`
16
17
18
19
20
21
22	134	jt_eaton
23			`gen_verilog`
24			`104.0`
25			`none`
26			`common`
27			`./tools/verilog/gen_verilog`
28
29
30			`destination`
31			`lifo_def`
32
33
34
35	131	jt_eaton
36
37
38
39
40
41
42
43
44
45
46
47
48
49			`Hierarchical`
50
51
52			`spirit:library="cde"`
53			`spirit:name="lifo"`
54			`spirit:version="def.design"/>`
55
56
57	134	jt_eaton
58			`verilog`
59
60
61			`spirit:library="Testbench"`
62			`spirit:name="toolflow"`
63			`spirit:version="verilog"/>`
64
65
66	131	jt_eaton
67
68	134	jt_eaton
69
70	131	jt_eaton
71	134	jt_eaton	`commoncommon`
72			`Verilog`
73
74
75			`fs-common`
76
77
78
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80
81
82
83
84	131	jt_eaton	`sim:Simulation:`
85
86			`Verilog`
87
88
89			`fs-sim`
90
91
92
93
94			`syn:Synthesis:`
95
96			`Verilog`
97
98
99			`fs-syn`
100
101
102
103
104			`doc`
105
106
107			`spirit:library="Testbench"`
108			`spirit:name="toolflow"`
109			`spirit:version="documentation"/>`
110
111			`:Documentation:`
112			`Verilog`
113
114
115
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117
118
119
120
121
122	134	jt_eaton
123
124
125
126
127
128
129
130
131			`fs-common`
132
133
134
135			`../verilog/lifo_def`
136			`verilogSourcefragment`
137
138
139
140
141
142			`../verilog/copyright`
143			`verilogSourceinclude`
144
145
146
147
148
149
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153
154
155			`fs-sim`
156
157
158
159			`../verilog/common/lifo_def`
160			`verilogSourcemodule`
161
162
163
164
165
166			`dest_dir`
167			`../views/sim/`
168			`verilogSourcelibraryDir`
169
170
171
172
173
174
175			`fs-syn`
176
177
178			`dest_dir`
179			`../views/sim/`
180			`verilogSourcelibraryDir`
181
182
183
184
185
186
187
188
189
190			`fs-lint`
191
192			`dest_dir`
193			`../views/sim/`
194			`verilogSourcelibraryDir`
195
196
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209	131	jt_eaton
210			`WIDTH8`
211			`SIZE2`
212			`WORDS4`
213	134	jt_eaton	`WRITETHRU1`
214	133	jt_eaton
215	134	jt_eaton
216	131	jt_eaton
217
218
219
220			`clk`
221			`wire`
222			`in`
223
224
225			`reset`
226			`wire`
227			`in`
228
229
230			`push`
231			`wire`
232			`in`
233
234
235			`pop`
236			`wire`
237			`in`
238
239
240
241
242
243			`din`
244			`wire`
245			`in`
246			`WIDTH-10`
247
248
249
250			`dout`
251	134	jt_eaton	`wire`
252	131	jt_eaton	`out`
253			`WIDTH-10`
254
255
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