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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_generic.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
mult
generic
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      mult_generic
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 
 
 
 
 
 

 
 
 
        
 
                        
                                verilog
                                verilog
                                cde_mult_generic
                                
                                        
                                                WIDTH
                                                16
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
 
 
  
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

WIDTH16

 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.generic
        verilogSourcefragment
      
 
 
  
 
 
   
      fs-sim
 
 
      
        ../verilog/common/mult_generic
        verilogSourcemodule
      
 
 
      
        ../verilog/or1200_gmultp2_32x32.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/mult_generic
        verilogSourcemodule
      
 
      
        ../verilog/or1200_gmultp2_32x32.v
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_generic.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`mult`
15			`generic`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22	135	jt_eaton
23			`gen_verilog`
24			`104.0`
25			`none`
26			`:common:`
27			`tools/verilog/gen_verilog`
28
29
30			`destination`
31			`mult_generic`
32
33
34
35	131	jt_eaton
36
37
38
39	135	jt_eaton
40			`gen_verilogLib_sim`
41			`105.0`
42			`none`
43			`:Simulation:`
44			`tools/verilog/gen_verilogLib`
45
46
47			`dest_dir`
48			`../views`
49
50
51			`view`
52			`sim`
53
54
55
56	131	jt_eaton
57
58
59	135	jt_eaton
60			`gen_verilogLib_syn`
61			`105.0`
62			`none`
63			`:Synthesis:`
64			`tools/verilog/gen_verilogLib`
65
66
67			`dest_dir`
68			`../views`
69
70
71			`view`
72			`syn`
73
74
75
76	131	jt_eaton
77
78
79	135	jt_eaton
80	131	jt_eaton
81
82
83
84
85
86
87
88	135	jt_eaton
89	131	jt_eaton
90
91
92	135	jt_eaton
93	131	jt_eaton
94	135	jt_eaton
95			`verilog`
96			`verilog`
97			`cde_mult_generic`
98
99
100			`WIDTH`
101			`16`
102
103
104
105			`fs-sim`
106
107
108
109	131	jt_eaton
110
111
112
113
114
115	135	jt_eaton
116	131	jt_eaton
117	135	jt_eaton
118			`rtl`
119			`verilog:Kactus2:`
120			`verilog`
121
122	131	jt_eaton
123	135	jt_eaton
124	131	jt_eaton
125	135	jt_eaton
126
127			`common:common:`
128
129			`Verilog`
130
131
132			`fs-common`
133
134
135	131	jt_eaton
136	135	jt_eaton
137			`sim:Simulation:`
138
139			`Verilog`
140
141
142			`fs-sim`
143
144
145	131	jt_eaton
146
147
148	135	jt_eaton
149			`syn:Synthesis:`
150
151			`Verilog`
152
153
154			`fs-syn`
155
156
157	131	jt_eaton
158
159
160	135	jt_eaton
161			`doc`
162
163
164			`ipxact:library="Testbench"`
165			`ipxact:name="toolflow"`
166			`ipxact:version="documentation"/>`
167
168			`:Documentation:`
169			`Verilog`
170
171	131	jt_eaton
172
173
174	135	jt_eaton
175	131	jt_eaton
176
177	135	jt_eaton
178			`WIDTH16`
179
180	131	jt_eaton
181
182
183
184	135	jt_eaton
185	131	jt_eaton
186	135	jt_eaton	`clk`
187			`wire`
188			`in`
189
190	131	jt_eaton
191	135	jt_eaton	`reset`
192			`wire`
193			`in`
194
195	131	jt_eaton
196
197
198
199
200
201	135	jt_eaton	`a_in`
202			`wire`
203			`in`
204			`WIDTH-10`
205
206	131	jt_eaton
207
208	135	jt_eaton	`b_in`
209			`wire`
210			`in`
211			`WIDTH-10`
212
213	131	jt_eaton
214
215	135	jt_eaton	`alu_op_mul`
216			`wire`
217			`in`
218
219	131	jt_eaton
220
221	135	jt_eaton	`ex_freeze`
222			`wire`
223			`in`
224
225	131	jt_eaton
226
227
228
229	135	jt_eaton	`mul_prod_r`
230			`reg`
231			`out`
232			`2*WIDTH-10`
233
234	131	jt_eaton
235
236	135	jt_eaton	`mul_stall`
237			`wire`
238			`out`
239
240	131	jt_eaton
241
242
243
244	135	jt_eaton
245	131	jt_eaton
246	135	jt_eaton
247	131	jt_eaton
248
249
250
251	135	jt_eaton
252	131	jt_eaton
253	135	jt_eaton
254			`fs-common`
255	131	jt_eaton
256
257	135	jt_eaton
258			`../verilog/top.generic`
259			`verilogSourcefragment`
260
261	131	jt_eaton
262
263	135	jt_eaton
264	131	jt_eaton
265
266	135	jt_eaton
267			`fs-sim`
268	131	jt_eaton
269
270	135	jt_eaton
271			`../verilog/common/mult_generic`
272			`verilogSourcemodule`
273
274	131	jt_eaton
275
276	135	jt_eaton
277			`../verilog/or1200_gmultp2_32x32.v`
278			`verilogSourcemodule`
279
280	131	jt_eaton
281	135	jt_eaton
282
283			`dest_dir../views/sim/`
284			`verilogSourcelibraryDir`
285
286	131	jt_eaton
287	135	jt_eaton
288	131	jt_eaton
289
290	135	jt_eaton
291			`fs-syn`
292	131	jt_eaton
293	135	jt_eaton
294			`../verilog/common/mult_generic`
295			`verilogSourcemodule`
296
297	131	jt_eaton
298	135	jt_eaton
299			`../verilog/or1200_gmultp2_32x32.v`
300			`verilogSourcemodule`
301
302	131	jt_eaton
303	135	jt_eaton
304			`dest_dir../views/syn/`
305			`verilogSourcelibraryDir`
306
307	131	jt_eaton
308
309
310	135	jt_eaton
311	131	jt_eaton
312
313	135	jt_eaton
314
315
316			`fs-lint`
317
318			`dest_dir../views/syn/`
319			`verilogSourcelibraryDir`
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334