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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
ord_r4  default
 
 
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.ord_r4
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.ord_r4
        verilogSourcefragment
      
 
  
 
   
      fs-sim
 
      
        ../verilog/common/top.ord_r4
        verilogSourcemodule
      
 
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/top.ord_r4
        verilogSourcemodule
      
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 
 

WIDTH32

 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4 default`
16
17
18
19
20
21
22
23
24
25
26			`gen_verilog`
27			`104.0`
28			`none`
29			`common`
30			`./tools/verilog/gen_verilog`
31
32
33			`destination`
34			`top.ord_r4`
35
36
37			`dest_dir`
38			`../verilog`
39
40
41
42
43
44
45
46
47			`gen_verilogLib_sim`
48			`105.0`
49			`none`
50			`:Simulation:`
51			`./tools/verilog/gen_verilogLib`
52
53
54			`dest_dir`
55			`../views`
56
57
58			`view`
59			`sim`
60
61
62
63
64
65
66			`gen_verilogLib_syn`
67			`105.0`
68			`none`
69			`:Synthesis:`
70			`./tools/verilog/gen_verilogLib`
71
72
73			`dest_dir`
74			`../views`
75
76
77			`view`
78			`syn`
79
80
81
82
83
84
85
86
87
88
89
90
91
92			`fs-common`
93
94
95
96			`../verilog/top.ord_r4`
97			`verilogSourcefragment`
98
99
100
101
102
103			`fs-sim`
104
105
106			`../verilog/common/top.ord_r4`
107			`verilogSourcemodule`
108
109
110
111
112			`../verilog/ord_r4.v`
113			`verilogSourcemodule`
114
115
116
117
118
119			`dest_dir../views/sim/`
120			`verilogSourcelibraryDir`
121
122
123
124
125
126
127			`fs-syn`
128
129
130			`../verilog/common/top.ord_r4`
131			`verilogSourcemodule`
132
133
134
135			`../verilog/ord_r4.v`
136			`verilogSourcemodule`
137
138
139
140
141			`dest_dir../views/syn/`
142			`verilogSourcelibraryDir`
143
144
145
146
147
148
149
150
151
152
153			`fs-lint`
154
155			`dest_dir../views/syn/`
156			`verilogSourcelibraryDir`
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`commoncommon`
178
179			`Verilog`
180
181
182			`fs-common`
183
184
185
186
187
188			`sim:Simulation:`
189
190			`Verilog`
191
192
193			`fs-sim`
194
195
196
197
198
199
200			`syn:Synthesis:`
201
202			`Verilog`
203
204
205			`fs-syn`
206
207
208
209
210
211			`doc`
212
213
214			`spirit:library="Testbench"`
215			`spirit:name="toolflow"`
216			`spirit:version="documentation"/>`
217
218			`:Documentation:`
219			`Verilog`
220
221
222
223
224
225
226
227
228
229
230
231			`WIDTH32`
232
233
234
235
236
237			`clk`
238			`wire`
239			`in`
240
241
242			`reset`
243			`wire`
244			`in`
245
246
247
248
249
250
251
252			`a_in`
253			`wire`
254			`in`
255			`WIDTH-10`
256
257
258
259			`b_in`
260			`wire`
261			`in`
262			`WIDTH-10`
263
264
265
266			`alu_op_mul`
267			`wire`
268			`in`
269
270
271
272			`ex_freeze`
273			`wire`
274			`in`
275
276
277
278
279
280			`mul_prod_r`
281			`reg`
282			`out`
283			`2*WIDTH-10`
284
285
286
287			`mul_stall`
288			`wire`
289			`out`
290
291
292
293
294
295
296
297
298
299
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303
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