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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
ord_r4  default
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.ord_r4
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.ord_r4
        verilogSourcefragment
      
 
  
 
   
      fs-sim
 
      
        ../verilog/common/top.ord_r4
        verilogSourcemodule
      
 
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/top.ord_r4
        verilogSourcemodule
      
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4 default`
16
17
18
19
20
21
22	133	jt_eaton
23			`elab_verilog`
24			`102.1`
25			`none`
26			`:Simulation:`
27			`./tools/verilog/elab_verilog`
28
29
30			`configuration`
31			`default`
32
33
34			`dest_dir`
35			`io_ports`
36
37
38
39	131	jt_eaton
40
41
42	133	jt_eaton
43	131	jt_eaton
44			`gen_verilog`
45			`104.0`
46			`none`
47			`common`
48			`./tools/verilog/gen_verilog`
49
50
51			`destination`
52			`top.ord_r4`
53
54
55			`dest_dir`
56			`../verilog`
57
58
59
60
61
62
63
64
65			`gen_verilogLib_sim`
66			`105.0`
67			`none`
68			`:Simulation:`
69			`./tools/verilog/gen_verilogLib`
70
71
72			`dest_dir`
73			`../views`
74
75
76			`view`
77			`sim`
78
79
80
81
82
83
84			`gen_verilogLib_syn`
85			`105.0`
86			`none`
87			`:Synthesis:`
88			`./tools/verilog/gen_verilogLib`
89
90
91			`dest_dir`
92			`../views`
93
94
95			`view`
96			`syn`
97
98
99
100
101
102
103
104
105
106
107
108
109
110			`fs-common`
111
112
113
114			`../verilog/top.ord_r4`
115			`verilogSourcefragment`
116
117
118
119
120
121			`fs-sim`
122
123
124			`../verilog/common/top.ord_r4`
125			`verilogSourcemodule`
126
127
128
129
130			`../verilog/ord_r4.v`
131			`verilogSourcemodule`
132
133
134
135
136
137			`dest_dir../views/sim/`
138			`verilogSourcelibraryDir`
139
140
141
142
143
144
145			`fs-syn`
146
147
148			`../verilog/common/top.ord_r4`
149			`verilogSourcemodule`
150
151
152
153			`../verilog/ord_r4.v`
154			`verilogSourcemodule`
155
156
157
158
159			`dest_dir../views/syn/`
160			`verilogSourcelibraryDir`
161
162
163
164
165
166
167
168
169
170
171			`fs-lint`
172
173			`dest_dir../views/syn/`
174			`verilogSourcelibraryDir`
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195			`commoncommon`
196
197			`Verilog`
198
199
200			`fs-common`
201
202
203
204
205
206			`sim:Simulation:`
207
208			`Verilog`
209
210
211			`fs-sim`
212
213
214
215
216
217
218			`syn:Synthesis:`
219
220			`Verilog`
221
222
223			`fs-syn`
224
225
226
227
228
229			`doc`
230
231
232			`spirit:library="Testbench"`
233			`spirit:name="toolflow"`
234			`spirit:version="documentation"/>`
235
236			`:Documentation:`
237			`Verilog`
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252			`clk`
253			`wire`
254			`in`
255
256
257			`reset`
258			`wire`
259			`in`
260
261
262
263
264
265
266
267			`a_in`
268			`wire`
269			`in`
270			`WIDTH-10`
271
272
273
274			`b_in`
275			`wire`
276			`in`
277			`WIDTH-10`
278
279
280
281			`alu_op_mul`
282			`wire`
283			`in`
284
285
286
287			`ex_freeze`
288			`wire`
289			`in`
290
291
292
293
294
295			`mul_prod_r`
296			`reg`
297			`out`
298			`2*WIDTH-10`
299
300
301
302			`mul_stall`
303			`wire`
304			`out`
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321