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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
ord_r4  default
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      mult_ord_r4
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.ord_r4
        verilogSourcefragment
      
 
  
 
   
      fs-sim
 
      
        ../verilog/common/mult_ord_r4
        verilogSourcemodule
      
 
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/mult_ord_r4
        verilogSourcemodule
      
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4 default`
16
17
18
19
20
21	133	jt_eaton
22	131	jt_eaton	`gen_verilog`
23			`104.0`
24			`none`
25			`common`
26			`./tools/verilog/gen_verilog`
27
28
29			`destination`
30	134	jt_eaton	`mult_ord_r4`
31	131	jt_eaton
32
33
34
35
36
37
38
39			`gen_verilogLib_sim`
40			`105.0`
41			`none`
42			`:Simulation:`
43			`./tools/verilog/gen_verilogLib`
44
45
46			`dest_dir`
47			`../views`
48
49
50			`view`
51			`sim`
52
53
54
55
56
57
58			`gen_verilogLib_syn`
59			`105.0`
60			`none`
61			`:Synthesis:`
62			`./tools/verilog/gen_verilogLib`
63
64
65			`dest_dir`
66			`../views`
67
68
69			`view`
70			`syn`
71
72
73
74
75
76
77
78
79
80
81
82
83
84			`fs-common`
85
86
87
88			`../verilog/top.ord_r4`
89			`verilogSourcefragment`
90
91
92
93
94
95			`fs-sim`
96
97
98	134	jt_eaton	`../verilog/common/mult_ord_r4`
99	131	jt_eaton	`verilogSourcemodule`
100
101
102
103
104			`../verilog/ord_r4.v`
105			`verilogSourcemodule`
106
107
108
109
110
111			`dest_dir../views/sim/`
112			`verilogSourcelibraryDir`
113
114
115
116
117
118
119			`fs-syn`
120
121
122	134	jt_eaton	`../verilog/common/mult_ord_r4`
123	131	jt_eaton	`verilogSourcemodule`
124
125
126
127			`../verilog/ord_r4.v`
128			`verilogSourcemodule`
129
130
131
132
133			`dest_dir../views/syn/`
134			`verilogSourcelibraryDir`
135
136
137
138
139
140
141
142
143
144
145			`fs-lint`
146
147			`dest_dir../views/syn/`
148			`verilogSourcelibraryDir`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169			`commoncommon`
170
171			`Verilog`
172
173
174			`fs-common`
175
176
177
178
179
180			`sim:Simulation:`
181
182			`Verilog`
183
184
185			`fs-sim`
186
187
188
189
190
191
192			`syn:Synthesis:`
193
194			`Verilog`
195
196
197			`fs-syn`
198
199
200
201
202
203			`doc`
204
205
206			`spirit:library="Testbench"`
207			`spirit:name="toolflow"`
208			`spirit:version="documentation"/>`
209
210			`:Documentation:`
211			`Verilog`
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226			`clk`
227			`wire`
228			`in`
229
230
231			`reset`
232			`wire`
233			`in`
234
235
236
237
238
239
240
241			`a_in`
242			`wire`
243			`in`
244			`WIDTH-10`
245
246
247
248			`b_in`
249			`wire`
250			`in`
251			`WIDTH-10`
252
253
254
255			`alu_op_mul`
256			`wire`
257			`in`
258
259
260
261			`ex_freeze`
262			`wire`
263			`in`
264
265
266
267
268
269			`mul_prod_r`
270			`reg`
271			`out`
272			`2*WIDTH-10`
273
274
275
276			`mul_stall`
277			`wire`
278			`out`
279
280
281
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283
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