URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
mult
serial
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      mult_serial
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 
 
 
 
 
 

 
 
 
        
 
                        
                                verilog
                                verilog
                                cde_mult_serial
                                
                                        
                                                WIDTH
                                                16
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
 
 
 
       
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

WIDTH16

 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 

 
   
      fs-common
 
      
        ../verilog/top.serial
        verilogSourcefragment
      
 
  
 
 
   
      fs-sim
 
      
        ../verilog/common/mult_serial
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/mult_serial
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`mult`
15			`serial`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21	135	jt_eaton
22			`gen_verilog`
23			`104.0`
24			`none`
25			`:common:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`mult_serial`
31
32
33
34	131	jt_eaton
35
36
37
38	135	jt_eaton
39			`gen_verilogLib_sim`
40			`105.0`
41			`none`
42			`:Simulation:`
43			`tools/verilog/gen_verilogLib`
44
45
46			`dest_dir`
47			`../views`
48
49
50			`view`
51			`sim`
52
53
54
55	131	jt_eaton
56
57	135	jt_eaton
58			`gen_verilogLib_syn`
59			`105.0`
60			`none`
61			`:Synthesis:`
62			`tools/verilog/gen_verilogLib`
63
64
65			`dest_dir`
66			`../views`
67
68
69			`view`
70			`syn`
71
72
73
74	131	jt_eaton
75
76
77	135	jt_eaton
78	131	jt_eaton
79
80
81
82
83
84
85
86	135	jt_eaton
87	131	jt_eaton
88
89
90	135	jt_eaton
91	131	jt_eaton
92	135	jt_eaton
93			`verilog`
94			`verilog`
95			`cde_mult_serial`
96
97
98			`WIDTH`
99			`16`
100
101
102
103			`fs-sim`
104
105
106
107	131	jt_eaton
108
109
110
111
112
113	135	jt_eaton
114
115	131	jt_eaton
116
117	135	jt_eaton
118			`rtl`
119			`verilog:Kactus2:`
120			`verilog`
121
122	131	jt_eaton
123	135	jt_eaton
124
125
126			`common:common:`
127
128			`Verilog`
129
130
131			`fs-common`
132
133
134	131	jt_eaton
135
136	135	jt_eaton
137			`sim:Simulation:`
138
139			`Verilog`
140
141
142			`fs-sim`
143
144
145	131	jt_eaton
146
147
148	135	jt_eaton
149			`syn:Synthesis:`
150
151			`Verilog`
152
153
154			`fs-syn`
155
156
157	131	jt_eaton
158
159	135	jt_eaton
160
161			`doc`
162
163
164			`ipxact:library="Testbench"`
165			`ipxact:name="toolflow"`
166			`ipxact:version="documentation"/>`
167
168			`:Documentation:`
169			`Verilog`
170
171	131	jt_eaton
172
173
174
175
176
177	135	jt_eaton
178	131	jt_eaton
179
180
181	135	jt_eaton
182			`WIDTH16`
183
184	131	jt_eaton
185
186
187
188
189	135	jt_eaton
190	131	jt_eaton
191	135	jt_eaton	`clk`
192			`wire`
193			`in`
194
195	131	jt_eaton
196	135	jt_eaton	`reset`
197			`wire`
198			`in`
199
200	131	jt_eaton
201
202
203
204
205
206	135	jt_eaton	`a_in`
207			`wire`
208			`in`
209			`WIDTH-10`
210
211	131	jt_eaton
212
213	135	jt_eaton	`b_in`
214			`wire`
215			`in`
216			`WIDTH-10`
217
218	131	jt_eaton
219
220	135	jt_eaton	`alu_op_mul`
221			`wire`
222			`in`
223
224	131	jt_eaton
225
226	135	jt_eaton	`ex_freeze`
227			`wire`
228			`in`
229
230	131	jt_eaton
231
232
233
234	135	jt_eaton	`mul_prod_r`
235			`reg`
236			`out`
237			`2*WIDTH-10`
238
239	131	jt_eaton
240
241	135	jt_eaton	`mul_stall`
242			`wire`
243			`out`
244
245	131	jt_eaton
246
247
248
249	135	jt_eaton
250	131	jt_eaton
251	135	jt_eaton
252	131	jt_eaton
253
254
255
256	135	jt_eaton
257	131	jt_eaton
258	135	jt_eaton
259			`fs-common`
260	131	jt_eaton
261	135	jt_eaton
262			`../verilog/top.serial`
263			`verilogSourcefragment`
264
265	131	jt_eaton
266	135	jt_eaton
267	131	jt_eaton
268
269	135	jt_eaton
270			`fs-sim`
271	131	jt_eaton
272	135	jt_eaton
273			`../verilog/common/mult_serial`
274			`verilogSourcemodule`
275
276
277
278			`dest_dir../views/sim/`
279			`verilogSourcelibraryDir`
280
281	131	jt_eaton
282	135	jt_eaton
283	131	jt_eaton
284
285	135	jt_eaton
286			`fs-syn`
287	131	jt_eaton
288	135	jt_eaton
289			`../verilog/common/mult_serial`
290			`verilogSourcemodule`
291
292	131	jt_eaton
293	135	jt_eaton
294			`dest_dir../views/syn/`
295			`verilogSourcelibraryDir`
296
297	131	jt_eaton
298
299	135	jt_eaton
300
301
302
303
304
305			`fs-lint`
306
307			`dest_dir../views/syn/`
308			`verilogSourcelibraryDir`
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323