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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
serial  default
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.serial
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
      
        ../verilog/top.serial
        verilogSourcefragment
      
 
  
 
 
   
      fs-sim
 
      
        ../verilog/common/top.serial
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/top.serial
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`serial default`
16
17
18
19
20
21	133	jt_eaton
22			`elab_verilog`
23			`102.1`
24			`none`
25			`:Simulation:`
26			`./tools/verilog/elab_verilog`
27
28
29			`configuration`
30			`default`
31
32
33			`dest_dir`
34			`io_ports`
35
36
37
38	131	jt_eaton
39	133	jt_eaton
40
41	131	jt_eaton
42			`gen_verilog`
43			`104.0`
44			`none`
45			`common`
46			`./tools/verilog/gen_verilog`
47
48
49			`destination`
50			`top.serial`
51
52
53			`dest_dir`
54			`../verilog`
55
56
57
58
59
60
61
62
63			`gen_verilogLib_sim`
64			`105.0`
65			`none`
66			`:Simulation:`
67			`./tools/verilog/gen_verilogLib`
68
69
70			`dest_dir`
71			`../views`
72
73
74			`view`
75			`sim`
76
77
78
79
80
81
82			`gen_verilogLib_syn`
83			`105.0`
84			`none`
85			`:Synthesis:`
86			`./tools/verilog/gen_verilogLib`
87
88
89			`dest_dir`
90			`../views`
91
92
93			`view`
94			`syn`
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`fs-common`
109
110
111			`../verilog/top.serial`
112			`verilogSourcefragment`
113
114
115
116
117
118
119			`fs-sim`
120
121
122			`../verilog/common/top.serial`
123			`verilogSourcemodule`
124
125
126
127			`dest_dir../views/sim/`
128			`verilogSourcelibraryDir`
129
130
131
132
133
134
135			`fs-syn`
136
137
138			`../verilog/common/top.serial`
139			`verilogSourcemodule`
140
141
142
143			`dest_dir../views/syn/`
144			`verilogSourcelibraryDir`
145
146
147
148
149
150
151
152
153
154			`fs-lint`
155
156			`dest_dir../views/syn/`
157			`verilogSourcelibraryDir`
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`commoncommon`
178
179			`Verilog`
180
181
182			`fs-common`
183
184
185
186
187
188			`sim:Simulation:`
189
190			`Verilog`
191
192
193			`fs-sim`
194
195
196
197
198
199
200			`syn:Synthesis:`
201
202			`Verilog`
203
204
205			`fs-syn`
206
207
208
209
210
211
212			`doc`
213
214
215			`spirit:library="Testbench"`
216			`spirit:name="toolflow"`
217			`spirit:version="documentation"/>`
218
219			`:Documentation:`
220			`Verilog`
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236			`clk`
237			`wire`
238			`in`
239
240
241			`reset`
242			`wire`
243			`in`
244
245
246
247
248
249
250
251			`a_in`
252			`wire`
253			`in`
254			`WIDTH-10`
255
256
257
258			`b_in`
259			`wire`
260			`in`
261			`WIDTH-10`
262
263
264
265			`alu_op_mul`
266			`wire`
267			`in`
268
269
270
271			`ex_freeze`
272			`wire`
273			`in`
274
275
276
277
278
279			`mul_prod_r`
280			`reg`
281			`out`
282			`2*WIDTH-10`
283
284
285
286			`mul_stall`
287			`wire`
288			`out`
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305