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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
serial  default
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      mult_serial
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
      
        ../verilog/top.serial
        verilogSourcefragment
      
 
  
 
 
   
      fs-sim
 
      
        ../verilog/common/mult_serial
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/mult_serial
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`serial default`
16
17
18
19
20
21	133	jt_eaton
22	131	jt_eaton	`gen_verilog`
23			`104.0`
24			`none`
25			`common`
26			`./tools/verilog/gen_verilog`
27
28
29			`destination`
30	134	jt_eaton	`mult_serial`
31	131	jt_eaton
32
33
34
35
36
37
38
39			`gen_verilogLib_sim`
40			`105.0`
41			`none`
42			`:Simulation:`
43			`./tools/verilog/gen_verilogLib`
44
45
46			`dest_dir`
47			`../views`
48
49
50			`view`
51			`sim`
52
53
54
55
56
57
58			`gen_verilogLib_syn`
59			`105.0`
60			`none`
61			`:Synthesis:`
62			`./tools/verilog/gen_verilogLib`
63
64
65			`dest_dir`
66			`../views`
67
68
69			`view`
70			`syn`
71
72
73
74
75
76
77
78
79
80
81
82
83
84			`fs-common`
85
86
87			`../verilog/top.serial`
88			`verilogSourcefragment`
89
90
91
92
93
94
95			`fs-sim`
96
97
98	134	jt_eaton	`../verilog/common/mult_serial`
99	131	jt_eaton	`verilogSourcemodule`
100
101
102
103			`dest_dir../views/sim/`
104			`verilogSourcelibraryDir`
105
106
107
108
109
110
111			`fs-syn`
112
113
114	134	jt_eaton	`../verilog/common/mult_serial`
115	131	jt_eaton	`verilogSourcemodule`
116
117
118
119			`dest_dir../views/syn/`
120			`verilogSourcelibraryDir`
121
122
123
124
125
126
127
128
129
130			`fs-lint`
131
132			`dest_dir../views/syn/`
133			`verilogSourcelibraryDir`
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153			`commoncommon`
154
155			`Verilog`
156
157
158			`fs-common`
159
160
161
162
163
164			`sim:Simulation:`
165
166			`Verilog`
167
168
169			`fs-sim`
170
171
172
173
174
175
176			`syn:Synthesis:`
177
178			`Verilog`
179
180
181			`fs-syn`
182
183
184
185
186
187
188			`doc`
189
190
191			`spirit:library="Testbench"`
192			`spirit:name="toolflow"`
193			`spirit:version="documentation"/>`
194
195			`:Documentation:`
196			`Verilog`
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212			`clk`
213			`wire`
214			`in`
215
216
217			`reset`
218			`wire`
219			`in`
220
221
222
223
224
225
226
227			`a_in`
228			`wire`
229			`in`
230			`WIDTH-10`
231
232
233
234			`b_in`
235			`wire`
236			`in`
237			`WIDTH-10`
238
239
240
241			`alu_op_mul`
242			`wire`
243			`in`
244
245
246
247			`ex_freeze`
248			`wire`
249			`in`
250
251
252
253
254
255			`mul_prod_r`
256			`reg`
257			`out`
258			`2*WIDTH-10`
259
260
261
262			`mul_stall`
263			`wire`
264			`out`
265
266
267
268
269
270
271
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273
274
275
276
277
278
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