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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_ord_r4_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
ord_r4_lint
 
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  103.0
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 
 

       
 
 
 
              
              Dut
              
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="ord_r4_dut.params"/>
              
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 

 
 
 

 
 
   
      fs-common
 
   
 
 
 
   
      fs-lint
 
      
        
        ../verilog/synthesys
        verilogSource
        include
      
 
 
      
        
        ../verilog/lint/mult_ord_r4_lint
        verilogSource
        module
      
 
 
   
 
 
 
 

 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4_lint`
16
17
18
19
20	133	jt_eaton
21	131	jt_eaton
22	133	jt_eaton
23			`elab_verilog`
24			`103.0`
25			`none`
26			`:Simulation:`
27			`>`
28			`./tools/verilog/elab_verilog`
29
30
31			`configuration`
32			`default`
33
34
35			`dest_dir`
36			`io_ports`
37
38
39
40	131	jt_eaton
41	133	jt_eaton
42			`gen_design`
43			`103.0`
44			`none`
45			`:Simulation:`
46			`>`
47			`./tools/verilog/gen_design`
48
49
50			`dest_dir`
51			`io_ports`
52
53
54
55	131	jt_eaton
56	133	jt_eaton
57	131	jt_eaton
58	133	jt_eaton
59
60
61
62	131	jt_eaton
63
64
65
66
67
68			`Dut`
69
70
71			`spirit:library="cde"`
72			`spirit:name="mult"`
73			`spirit:version="ord_r4_dut.params"/>`
74
75
76
77
78
79
80			`lint`
81			`:Lint:`
82			`Verilog`
83			`fs-lint`
84
85
86
87
88
89			`rtl_check`
90
91
92			`spirit:library="Testbench"`
93			`spirit:name="toolflow"`
94			`spirit:version="rtl_check"/>`
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110			`fs-common`
111
112
113
114
115
116
117			`fs-lint`
118
119
120
121			`../verilog/synthesys`
122			`verilogSource`
123			`include`
124
125
126
127
128
129			`../verilog/lint/mult_ord_r4_lint`
130			`verilogSource`
131			`module`
132
133
134
135
136
137
138
139
140
141
142
143
144

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_ord_r4_lint.xml] - Blame information for rev 133