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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_ord_r4_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
mult
ord_r4_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      mult_ord_r4_tb
    
  

 
 
 
 

 
 
 
 
 
 
 
 

       
 
 
 
              
              Params
              
              
                                   ipxact:library="cde"
                                   ipxact:name="mult"
                                   ipxact:version="ord_r4_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   ipxact:library="cde"
                                   ipxact:name="mult"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 

 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/top
        verilogSourcefragment
      
 
   
 
   
      fs-sim
 
      
        
        ../verilog/common/mult_ord_r4_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/synthesys
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/mult_ord_r4_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`mult_ord_r4_tb`
34
35
36
37	131	jt_eaton
38
39
40
41	135	jt_eaton
42	131	jt_eaton
43
44
45
46
47
48
49
50	135	jt_eaton
51
52	131	jt_eaton
53
54
55	135	jt_eaton
56			`Params`
57
58
59			`ipxact:library="cde"`
60			`ipxact:name="mult"`
61			`ipxact:version="ord_r4_dut.params"/>`
62
63
64	131	jt_eaton
65
66
67
68	135	jt_eaton
69			`Bfm`
70
71			`ipxact:library="cde"`
72			`ipxact:name="mult"`
73			`ipxact:version="bfm.design"/>`
74
75	131	jt_eaton
76
77
78	135	jt_eaton
79			`icarus`
80
81
82			`ipxact:library="Testbench"`
83			`ipxact:name="toolflow"`
84			`ipxact:version="icarus"/>`
85
86
87	131	jt_eaton
88
89
90
91	135	jt_eaton
92			`common:common:`
93			`Verilog`
94
95
96			`fs-common`
97
98
99	131	jt_eaton
100	135	jt_eaton
101			`sim:Simulation:`
102			`Verilog`
103
104
105			`fs-sim`
106
107
108	131	jt_eaton
109
110
111	135	jt_eaton
112			`lint:Lint:`
113			`Verilog`
114
115
116			`fs-lint`
117
118
119	131	jt_eaton
120	135	jt_eaton
121	131	jt_eaton
122
123
124
125
126	135	jt_eaton
127	131	jt_eaton
128
129
130
131	135	jt_eaton
132	131	jt_eaton
133
134	135	jt_eaton
135			`fs-common`
136	131	jt_eaton
137	135	jt_eaton
138
139			`../verilog/top`
140			`verilogSourcefragment`
141
142	131	jt_eaton
143	135	jt_eaton
144	131	jt_eaton
145	135	jt_eaton
146			`fs-sim`
147	131	jt_eaton
148	135	jt_eaton
149
150			`../verilog/common/mult_ord_r4_tb`
151			`verilogSourcemodule`
152
153	131	jt_eaton
154
155	135	jt_eaton
156	131	jt_eaton
157
158	135	jt_eaton
159			`fs-lint`
160	131	jt_eaton
161	135	jt_eaton
162
163			`../verilog/synthesys`
164			`verilogSourceinclude`
165
166	131	jt_eaton
167
168	135	jt_eaton
169
170			`../verilog/common/mult_ord_r4_tb`
171			`verilogSourcemodule`
172
173	131	jt_eaton
174
175
176	135	jt_eaton
177	131	jt_eaton
178
179
180
181	135	jt_eaton
182	131	jt_eaton
183
184
185
186	135	jt_eaton

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_ord_r4_tb.xml] - Blame information for rev 135