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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_ord_r4_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
ord_r4_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.ord_r4_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 

 
 
 
 
 
 
 
 

       
 
 
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="ord_r4_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 

 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/top
        verilogSourcefragment
      
 
   
 
   
      fs-sim
 
      
        
        ../verilog/common/top.ord_r4_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/synthesys
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.ord_r4_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33			`top.ord_r4_tb`
34
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
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61
62
63			`Params`
64
65
66			`spirit:library="cde"`
67			`spirit:name="mult"`
68			`spirit:version="ord_r4_dut.params"/>`
69
70
71
72
73
74
75
76			`Bfm`
77
78			`spirit:library="cde"`
79			`spirit:name="mult"`
80			`spirit:version="bfm.design"/>`
81
82
83
84
85
86			`icarus`
87
88
89			`spirit:library="Testbench"`
90			`spirit:name="toolflow"`
91			`spirit:version="icarus"/>`
92
93
94
95
96
97
98
99			`commoncommon`
100			`Verilog`
101
102
103			`fs-common`
104
105
106
107
108			`sim:Simulation:`
109			`Verilog`
110
111
112			`fs-sim`
113
114
115
116
117
118
119			`lint:Lint:`
120			`Verilog`
121
122
123			`fs-lint`
124
125
126
127
128
129
130
131
132
133
134
135
136
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141
142			`fs-common`
143
144
145
146			`../verilog/top`
147			`verilogSourcefragment`
148
149
150
151
152
153			`fs-sim`
154
155
156
157			`../verilog/common/top.ord_r4_tb`
158			`verilogSourcemodule`
159
160
161
162
163
164
165
166			`fs-lint`
167
168
169
170			`../verilog/synthesys`
171			`verilogSourceinclude`
172
173
174
175
176
177			`../verilog/common/top.ord_r4_tb`
178			`verilogSourcemodule`
179
180
181
182
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185
186
187
188
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_ord_r4_tb.xml] - Blame information for rev 133