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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_serial_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
serial_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      mult_serial_tb
    
  

 
 
 

 
 
 
 
 
 
 
 

       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="serial_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top
        verilogSourcefragment
      
 
   
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/mult_serial_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 
   
      fs-lint
 
      
        
        ../verilog/synthesys
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/mult_serial_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 

 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`serial_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	134	jt_eaton	`mult_serial_tb`
34	131	jt_eaton
35
36
37
38
39
40
41
42
43
44
45
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47
48
49
50
51
52
53			`Params`
54
55
56			`spirit:library="cde"`
57			`spirit:name="mult"`
58			`spirit:version="serial_dut.params"/>`
59
60
61
62
63
64			`Bfm`
65
66			`spirit:library="cde"`
67			`spirit:name="mult"`
68			`spirit:version="bfm.design"/>`
69
70
71
72
73
74			`icarus`
75
76
77			`spirit:library="Testbench"`
78			`spirit:name="toolflow"`
79			`spirit:version="icarus"/>`
80
81
82
83
84
85
86
87			`commoncommon`
88			`Verilog`
89
90
91			`fs-common`
92
93
94
95
96			`sim:Simulation:`
97			`Verilog`
98
99
100			`fs-sim`
101
102
103
104
105
106			`lint:Lint:`
107			`Verilog`
108
109
110			`fs-lint`
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127			`fs-common`
128
129
130
131			`../verilog/top`
132			`verilogSourcefragment`
133
134
135
136
137
138			`fs-sim`
139
140
141
142
143
144	134	jt_eaton	`../verilog/common/mult_serial_tb`
145	131	jt_eaton	`verilogSourcemodule`
146
147
148
149
150
151
152
153
154
155
156			`fs-lint`
157
158
159
160			`../verilog/synthesys`
161			`verilogSourceinclude`
162
163
164
165
166
167	134	jt_eaton	`../verilog/common/mult_serial_tb`
168	131	jt_eaton	`verilogSourcemodule`
169
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_serial_tb.xml] - Blame information for rev 134