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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [mult_ord_r4_dutg.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
cde
mult
ord_r4_dutg.design
 
 
 

 

clk



 

reset



 
 

a_in



 

b_in



 
 
 

alu_op_mul



 
 
 

ex_freeze



 

mul_prod_r



 

mul_stall



 
 
 


 

dut


 WIDTH





Line No.	Rev	Author	Line
1	131	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`cde`
17			`mult`
18			`ord_r4_dutg.design`
19	131	jt_eaton
20
21
22	135	jt_eaton
23	131	jt_eaton
24	135	jt_eaton
25			`clk`
26
27
28
29	131	jt_eaton
30	135	jt_eaton
31			`reset`
32
33
34
35	131	jt_eaton
36
37	135	jt_eaton
38			`a_in`
39
40
41
42	131	jt_eaton
43	135	jt_eaton
44			`b_in`
45
46
47
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`alu_op_mul`
53
54
55
56	131	jt_eaton
57
58
59	135	jt_eaton
60			`ex_freeze`
61
62
63
64	131	jt_eaton
65	135	jt_eaton
66			`mul_prod_r`
67
68
69
70	131	jt_eaton
71	135	jt_eaton
72			`mul_stall`
73
74
75
76	131	jt_eaton
77
78
79	135	jt_eaton
80
81	131	jt_eaton
82	135	jt_eaton
83			`dut`
84
85
86			`WIDTH`
87
88
89
90

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [mult_ord_r4_dutg.design.xml] - Blame information for rev 135