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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [verilog/] [pad_se_dig] - Blame information for rev 135

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assign           pad_in  = PAD;
 
 
 
generate
    genvar                  i;
 
  if(SCMD)
    begin
    assign           PAD     = pad_oe[0] ? pad_out  : {WIDTH{1'bz}};
    end
  else
    begin
    for (i=0; i < WIDTH; i=i+1)
      begin:m
      assign           PAD[i]     = pad_oe[i] ? pad_out[i]  : {1'bz};
      end
    end
 
endgenerate
 
 
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`assign pad_in = PAD;`
2	135	jt_eaton
3
4
5			`generate`
6			`genvar i;`
7
8			`if(SCMD)`
9			`begin`
10			`assign PAD = pad_oe[0] ? pad_out : {WIDTH{1'bz}};`
11			`end`
12			`else`
13			`begin`
14			`for (i=0; i < WIDTH; i=i+1)`
15			`begin:m`
16			`assign PAD[i] = pad_oe[i] ? pad_out[i] : {1'bz};`
17			`end`
18			`end`
19
20			`endgenerate`
21	134	jt_eaton
22
23
24	135	jt_eaton
25

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [verilog/] [pad_se_dig] - Blame information for rev 135