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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
in_dig  default
 
 
 
 

 
 pad_ring
  
  
  
    
      
        PAD_in
        PAD
        
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_in
        pad_in
        
      
 
    
 
 
 
 
 
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      pad_in_dig
    
  

 
 
 
 

 
 
 

       
 
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 

WIDTH1

 
 
 

 
PAD
wire
in
WIDTH-10

 
pad_in
wire
out
WIDTH-10

 
 
 
 
 
 
 
 

 

 
 
 
 
 

 
 
 
 
      fs-common
 
      
        
        ../verilog/pad_in_dig
        verilogSourcefragment
      
 
   
 
 
 
   
      fs-sim
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_in_dig
        verilogSourcemodule
      
 
 
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_in_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`in_dig default`
16
17
18
19
20
21
22			`pad_ring`
23
24
25
26
27
28			`PAD_in`
29			`PAD`
30
31
32
33
34
35
36
37
38			`pad`
39
40
41
42
43
44			`pad_in`
45			`pad_in`
46
47
48
49
50
51
52
53
54
55
56
57
58
59	134	jt_eaton
60	131	jt_eaton
61
62
63	134	jt_eaton
64
65			`gen_verilog`
66			`104.0`
67			`none`
68			`common`
69			`./tools/verilog/gen_verilog`
70
71
72			`destination`
73			`pad_in_dig`
74
75
76
77
78
79
80
81
82
83
84
85	131	jt_eaton
86
87
88
89	134	jt_eaton
90			`verilog`
91
92
93			`spirit:library="Testbench"`
94			`spirit:name="toolflow"`
95			`spirit:version="verilog"/>`
96
97
98	131	jt_eaton
99	134	jt_eaton
100
101	131	jt_eaton
102	134	jt_eaton	`commoncommon`
103			`Verilog`
104
105
106			`fs-common`
107
108
109
110
111
112	131	jt_eaton	`sim:Simulation:`
113			`Verilog`
114
115
116			`fs-sim`
117
118
119
120
121			`syn:Synthesis:`
122			`Verilog`
123
124
125			`fs-syn`
126
127
128
129
130			`doc`
131
132
133			`spirit:library="Testbench"`
134			`spirit:name="toolflow"`
135			`spirit:version="documentation"/>`
136
137			`:Documentation:`
138			`Verilog`
139
140
141
142
143
144
145			`WIDTH1`
146
147
148
149
150
151
152			`PAD`
153			`wire`
154			`in`
155			`WIDTH-10`
156
157
158			`pad_in`
159			`wire`
160			`out`
161			`WIDTH-10`
162
163
164
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166
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172
173
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175
176
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178
179
180
181	134	jt_eaton
182
183
184			`fs-common`
185
186
187
188			`../verilog/pad_in_dig`
189			`verilogSourcefragment`
190
191
192
193
194
195
196	131	jt_eaton
197			`fs-sim`
198
199	134	jt_eaton
200
201
202			`../verilog/copyright`
203			`verilogSourceinclude`
204
205
206
207
208
209			`../verilog/common/pad_in_dig`
210			`verilogSourcemodule`
211
212
213
214
215	131	jt_eaton
216			`dest_dir`
217	134	jt_eaton	`../views/sim/`
218	131	jt_eaton	`verilogSourcelibraryDir`
219
220
221
222
223
224
225			`fs-syn`
226	134	jt_eaton
227
228
229
230			`../verilog/copyright`
231			`verilogSourceinclude`
232
233
234
235	131	jt_eaton
236	134	jt_eaton
237			`../verilog/common/pad_in_dig`
238			`verilogSourcemodule`
239
240
241
242
243	131	jt_eaton	`dest_dir`
244	134	jt_eaton	`../views/syn/`
245	131	jt_eaton	`verilogSourcelibraryDir`
246
247
248
249
250
251
252
253
254
255
256			`fs-lint`
257
258			`dest_dir`
259	134	jt_eaton	`../views/syn/`
260	131	jt_eaton	`verilogSourcelibraryDir`
261
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