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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_od_dig.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
od_dig  default
 
 
 
 
 
 

 
 pad_ring
  
  
  
    
      
        PAD_io
        PAD
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_oe
        pad_oe
      
      
        pad_in
        pad_in
      
 
    
 
 
 
 
 
 

 
 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      pad_od_dig
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  
    
      destination
      pad_od_dig
    
  

 
 
 
 

 
 
 
 

       
 
            
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
PAD
wire
inout

 
pad_in
wire
out

 
pad_oe
wire
in

 
 

 

 
 
 
 

 
   
      fs-sim
 
     
        
        ../verilog/pad_od_sim
        verilogSourcefragment
      
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/pad_od_dig
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
     
        
        ../verilog/pad_od_syn
        verilogSourcefragment
      
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/pad_od_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_od_dig.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`od_dig default`
16
17
18
19
20
21
22
23
24			`pad_ring`
25
26
27
28
29
30			`PAD_io`
31			`PAD`
32
33
34
35
36
37
38
39			`pad`
40
41
42
43
44
45			`pad_oe`
46			`pad_oe`
47
48
49			`pad_in`
50			`pad_in`
51
52
53
54
55
56
57
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61
62
63
64
65	134	jt_eaton
66	131	jt_eaton
67
68
69	134	jt_eaton
70
71			`gen_verilog_sim`
72			`104.0`
73			`none`
74			`:Simulation:`
75			`./tools/verilog/gen_verilog`
76
77
78			`destination`
79			`pad_od_dig`
80
81
82
83
84
85
86			`gen_verilog_syn`
87			`104.0`
88			`none`
89			`:Synthesis:`
90			`./tools/verilog/gen_verilog`
91
92
93			`destination`
94			`pad_od_dig`
95
96
97
98
99
100
101
102
103
104
105
106
107	131	jt_eaton
108
109
110	134	jt_eaton
111			`verilog`
112
113
114			`spirit:library="Testbench"`
115			`spirit:name="toolflow"`
116			`spirit:version="verilog"/>`
117
118
119	131	jt_eaton
120
121	134	jt_eaton
122
123
124
125	131	jt_eaton
126			`sim:Simulation:`
127			`Verilog`
128
129
130			`fs-sim`
131
132
133
134
135			`syn:Synthesis:`
136			`Verilog`
137
138
139			`fs-syn`
140
141
142
143
144
145
146			`doc`
147
148
149			`spirit:library="Testbench"`
150			`spirit:name="toolflow"`
151			`spirit:version="documentation"/>`
152
153			`:Documentation:`
154			`Verilog`
155
156
157
158
159
160
161
162
163
164
165			`PAD`
166			`wire`
167			`inout`
168
169
170			`pad_in`
171			`wire`
172			`out`
173
174
175			`pad_oe`
176			`wire`
177			`in`
178
179
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181
182
183
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185
186
187
188
189
190
191			`fs-sim`
192
193	134	jt_eaton
194
195			`../verilog/pad_od_sim`
196			`verilogSourcefragment`
197
198
199
200
201			`../verilog/copyright`
202			`verilogSourceinclude`
203
204
205	131	jt_eaton
206	134	jt_eaton
207			`../verilog/sim/pad_od_dig`
208			`verilogSourcemodule`
209
210
211
212
213
214	131	jt_eaton	`dest_dir`
215	134	jt_eaton	`../views/sim/`
216	131	jt_eaton	`verilogSourcelibraryDir`
217
218
219
220
221
222
223			`fs-syn`
224
225	134	jt_eaton
226
227			`../verilog/pad_od_syn`
228			`verilogSourcefragment`
229
230
231
232
233			`../verilog/copyright`
234			`verilogSourceinclude`
235
236
237	131	jt_eaton
238	134	jt_eaton
239			`../verilog/syn/pad_od_dig`
240			`verilogSourcemodule`
241
242
243
244
245	131	jt_eaton	`dest_dir`
246	134	jt_eaton	`../views/syn/`
247	131	jt_eaton	`verilogSourcelibraryDir`
248
249
250
251
252
253
254
255
256
257			`fs-lint`
258
259			`dest_dir`
260	134	jt_eaton	`../views/syn/`
261	131	jt_eaton	`verilogSourcelibraryDir`
262
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