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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_dig.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
out_dig
 
 
 
 
 

 
 pad_ring
  
 
 
  
      
  
          
            
        PAD_out
        PAD
            
          
        
      
  
 
 
 
 
 pad
  
  
      
  
          
            
        pad_out
        pad_out 
            
          
        
      
  
 
 

 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_out_dig
    
  

 
 
 
 

 
 

 
 
 
 
 
 
 
                
                        
                                verilog
                                verilog
                                cde_pad_out_dig
                                
                                        
                                                WIDTH
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
 
 
 
  
 
 
                
                                rtl
                                verilog:Kactus2:
                                verilog
                
 
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
                
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

WIDTH1

 
 

 
PAD
wire
out
WIDTH-10

 
pad_out
wire
in
WIDTH-10

 

 

 
 
 
 
 
 
 

 
 
 
 
      fs-common
 
      
        
        ../verilog/pad_out_dig
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_out_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_out_dig
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 

 
 

 
 
 
 
 
 
 
 

refdes
P?
600
700
5
10
1
1
2

 

module_name
cde_pad_out_dig
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
pad
0
-400
0
10
0
0
0

 
 
 

version
out_dig
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_pad_out_dig
 
 

 geda-project.org
 symbols
 pads
 def
 out_pad
 100
 200

 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 400
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1300
 400
 PAD
 0

 
 

 
 
 
 

vector
 
 

 geda-project.org
 symbols
 pads
 def
 out_pad
 100
 200

 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 400
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 400
 PAD
 0

 
 

 
 
 
 
 
 
 

 
 


 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_dig.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`pad`
15			`out_dig`
16	131	jt_eaton
17
18
19
20
21	135	jt_eaton
22	131	jt_eaton
23	135	jt_eaton	`pad_ring`
24
25	131	jt_eaton
26
27	135	jt_eaton
28
29
30
31
32			`PAD_out`
33			`PAD`
34
35
36
37
38
39
40	131	jt_eaton
41
42
43	135	jt_eaton	`pad`
44
45
46
47
48
49
50			`pad_out`
51			`pad_out`
52
53
54
55
56
57
58	131	jt_eaton
59	135	jt_eaton
60	131	jt_eaton
61
62
63	135	jt_eaton
64	131	jt_eaton
65
66
67
68	135	jt_eaton
69			`gen_verilog`
70			`104.0`
71			`none`
72			`:common:`
73			`tools/verilog/gen_verilog`
74
75
76			`destination`
77			`pad_out_dig`
78
79
80
81	131	jt_eaton
82	134	jt_eaton
83
84
85	135	jt_eaton
86	134	jt_eaton
87
88	135	jt_eaton
89	134	jt_eaton
90
91
92	131	jt_eaton
93
94	134	jt_eaton
95
96	135	jt_eaton
97
98			`verilog`
99			`verilog`
100			`cde_pad_out_dig`
101
102
103			`WIDTH`
104			`1`
105
106
107
108			`fs-sim`
109
110
111
112	134	jt_eaton
113
114
115	131	jt_eaton
116
117
118
119	135	jt_eaton
120	131	jt_eaton
121
122	135	jt_eaton
123			`rtl`
124			`verilog:Kactus2:`
125			`verilog`
126
127	131	jt_eaton
128	135	jt_eaton
129
130			`verilog`
131
132
133			`ipxact:library="Testbench"`
134			`ipxact:name="toolflow"`
135			`ipxact:version="verilog"/>`
136
137
138	131	jt_eaton
139
140
141	135	jt_eaton
142			`common:common:`
143			`Verilog`
144
145
146			`fs-common`
147
148
149	131	jt_eaton
150
151	135	jt_eaton
152			`sim:Simulation:`
153			`Verilog`
154
155
156			`fs-sim`
157
158
159	131	jt_eaton
160	135	jt_eaton
161			`syn:Synthesis:`
162			`Verilog`
163
164
165			`fs-syn`
166
167
168	131	jt_eaton
169	135	jt_eaton
170			`doc`
171
172
173			`ipxact:library="Testbench"`
174			`ipxact:name="toolflow"`
175			`ipxact:version="documentation"/>`
176
177			`:Documentation:`
178			`Verilog`
179
180	131	jt_eaton
181
182
183	135	jt_eaton
184	131	jt_eaton
185
186	135	jt_eaton
187			`WIDTH1`
188
189	131	jt_eaton
190
191	135	jt_eaton
192	134	jt_eaton
193	135	jt_eaton	`PAD`
194			`wire`
195			`out`
196			`WIDTH-10`
197
198	134	jt_eaton
199	135	jt_eaton	`pad_out`
200			`wire`
201			`in`
202			`WIDTH-10`
203
204	134	jt_eaton
205	135	jt_eaton
206	134	jt_eaton
207	135	jt_eaton
208	134	jt_eaton
209
210	131	jt_eaton
211	134	jt_eaton
212
213
214
215	135	jt_eaton
216	131	jt_eaton
217
218
219	135	jt_eaton
220			`fs-common`
221	131	jt_eaton
222	135	jt_eaton
223
224			`../verilog/pad_out_dig`
225			`verilogSourcefragment`
226
227	134	jt_eaton
228	135	jt_eaton
229	134	jt_eaton
230
231	135	jt_eaton
232			`fs-sim`
233	134	jt_eaton
234	135	jt_eaton
235
236			`../verilog/copyright`
237			`verilogSourceinclude`
238
239	134	jt_eaton
240	131	jt_eaton
241	135	jt_eaton
242
243			`../verilog/common/pad_out_dig`
244			`verilogSourcemodule`
245
246	131	jt_eaton
247
248	135	jt_eaton
249			`dest_dir`
250			`../views/sim/`
251			`verilogSourcelibraryDir`
252
253	131	jt_eaton
254	135	jt_eaton
255	131	jt_eaton
256
257	135	jt_eaton
258			`fs-syn`
259	131	jt_eaton
260	135	jt_eaton
261
262			`../verilog/copyright`
263			`verilogSourceinclude`
264
265	131	jt_eaton
266
267	135	jt_eaton
268
269			`../verilog/common/pad_out_dig`
270			`verilogSourcemodule`
271
272	131	jt_eaton
273
274
275	135	jt_eaton
276			`dest_dir`
277			`../views/syn/`
278			`verilogSourcelibraryDir`
279
280	131	jt_eaton
281
282
283	135	jt_eaton
284	131	jt_eaton
285
286	135	jt_eaton
287	131	jt_eaton
288	135	jt_eaton	`fs-lint`
289
290			`dest_dir`
291			`../views/syn/`
292			`verilogSourcelibraryDir`
293
294	131	jt_eaton
295	135	jt_eaton
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319			`refdes`
320			`P?`
321			`600`
322			`700`
323			`5`
324			`10`
325			`1`
326			`1`
327			`2`
328
329
330
331			`module_name`
332			`cde_pad_out_dig`
333			`400`
334			`0`
335			`5`
336			`10`
337			`0`
338			`1`
339			`2`
340
341
342
343			`vendor`
344			`opencores.org`
345			`0`
346			`-200`
347			`0`
348			`10`
349			`0`
350			`0`
351			`0`
352
353
354
355			`library`
356			`cde`
357			`0`
358			`-300`
359			`0`
360			`10`
361			`0`
362			`0`
363			`0`
364
365
366
367
368			`component`
369			`pad`
370			`0`
371			`-400`
372			`0`
373			`10`
374			`0`
375			`0`
376			`0`
377
378
379
380
381
382			`version`
383			`out_dig`
384			`0`
385			`-500`
386			`0`
387			`10`
388			`0`
389			`0`
390			`0`
391
392
393
394
395
396
397
398
399
400
401
402
403			`cde_pad_out_dig`
404
405
406
407			`geda-project.org`
408			`symbols`
409			`pads`
410			`def`
411			`out_pad`
412			`100`
413			`200`
414
415
416
417			`geda-project.org`
418			`symbols`
419			`pins`
420			`def`
421			`in_wire`
422			`0`
423			`400`
424			`pad_out`
425			`0`
426
427
428
429
430			`geda-project.org`
431			`symbols`
432			`pins`
433			`def`
434			`out_wire`
435			`1300`
436			`400`
437			`PAD`
438			`0`
439
440
441
442
443
444
445
446
447
448			`vector`
449
450
451
452			`geda-project.org`
453			`symbols`
454			`pads`
455			`def`
456			`out_pad`
457			`100`
458			`200`
459
460
461
462			`geda-project.org`
463			`symbols`
464			`pins`
465			`def`
466			`in_bus`
467			`0`
468			`400`
469			`pad_out`
470			`0`
471
472
473
474
475			`geda-project.org`
476			`symbols`
477			`pins`
478			`def`
479			`out_bus`
480			`1300`
481			`400`
482			`PAD`
483			`0`
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511