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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_dig.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
out_dig  default
 
 
 
 
 

 
 pad_ring
  
  
  
    
      
        PAD_out
        PAD
        
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_out
        pad_out
      
      
    
 
 
 
 
 
 

 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      pad_out_dig
    
  

 
 
 
 

 
 

       
 
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
                
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

WIDTH1

 
 

 
PAD
wire
out
WIDTH-10

 
pad_out
wire
in
WIDTH-10

 

 

 
 
 
 
 
 
 

 
 
 
 
      fs-common
 
      
        
        ../verilog/pad_out_dig
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_out_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_out_dig
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_dig.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`out_dig default`
16
17
18
19
20
21
22
23			`pad_ring`
24
25
26
27
28
29			`PAD_out`
30			`PAD`
31
32
33
34
35
36
37
38
39			`pad`
40
41
42
43
44
45			`pad_out`
46			`pad_out`
47
48
49
50
51
52
53
54
55
56
57
58
59
60	134	jt_eaton
61	131	jt_eaton
62
63	134	jt_eaton
64
65
66			`gen_verilog`
67			`104.0`
68			`none`
69			`common`
70			`./tools/verilog/gen_verilog`
71
72
73			`destination`
74			`pad_out_dig`
75
76
77
78
79
80
81
82
83
84
85	131	jt_eaton
86
87
88
89	134	jt_eaton
90			`verilog`
91
92
93			`spirit:library="Testbench"`
94			`spirit:name="toolflow"`
95			`spirit:version="verilog"/>`
96
97
98
99
100
101	131	jt_eaton
102	134	jt_eaton	`commoncommon`
103			`Verilog`
104
105
106			`fs-common`
107
108
109
110
111
112	131	jt_eaton	`sim:Simulation:`
113			`Verilog`
114
115
116			`fs-sim`
117
118
119
120
121			`syn:Synthesis:`
122			`Verilog`
123
124
125			`fs-syn`
126
127
128
129
130			`doc`
131
132
133			`spirit:library="Testbench"`
134			`spirit:name="toolflow"`
135			`spirit:version="documentation"/>`
136
137			`:Documentation:`
138			`Verilog`
139
140
141
142
143
144
145
146
147			`WIDTH1`
148
149
150
151
152
153			`PAD`
154			`wire`
155			`out`
156			`WIDTH-10`
157
158
159			`pad_out`
160			`wire`
161			`in`
162			`WIDTH-10`
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177	134	jt_eaton
178
179
180			`fs-common`
181
182
183
184			`../verilog/pad_out_dig`
185			`verilogSourcefragment`
186
187
188
189
190
191	131	jt_eaton
192			`fs-sim`
193
194	134	jt_eaton
195
196			`../verilog/copyright`
197			`verilogSourceinclude`
198
199
200
201	131	jt_eaton
202	134	jt_eaton
203			`../verilog/common/pad_out_dig`
204			`verilogSourcemodule`
205
206
207
208
209	131	jt_eaton	`dest_dir`
210	134	jt_eaton	`../views/sim/`
211	131	jt_eaton	`verilogSourcelibraryDir`
212
213
214
215
216
217
218			`fs-syn`
219
220	134	jt_eaton
221
222			`../verilog/copyright`
223			`verilogSourceinclude`
224
225
226
227	131	jt_eaton
228	134	jt_eaton
229			`../verilog/common/pad_out_dig`
230			`verilogSourcemodule`
231
232
233
234
235
236	131	jt_eaton	`dest_dir`
237	134	jt_eaton	`../views/syn/`
238	131	jt_eaton	`verilogSourcelibraryDir`
239
240
241
242
243
244
245
246
247
248			`fs-lint`
249
250			`dest_dir`
251	134	jt_eaton	`../views/syn/`
252	131	jt_eaton	`verilogSourcelibraryDir`
253
254
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