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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_tri_dig.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
tri_dig  default
 

 
 pad_ring
  
  
  
    
      
        PAD_out
        PAD
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_out
        pad_out
      
      
        pad_oe
        pad_oe
      
 
    
 
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      pad_tri_dig
    
  

 
 
 
 

 
 
 

       
 
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
PAD
wire
inout

 
pad_out
wire
in

 
pad_oe
wire
in

 
 
 
 
 

 

 
 

 
 
 
      fs-common
 
      
        
        ../verilog/pad_tri_dig
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
 
 
 
 
 
   
      fs-sim
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_tri_dig
        verilogSourcemodule
      
 
 
 
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_tri_dig
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_tri_dig.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`tri_dig default`
16
17
18
19			`pad_ring`
20
21
22
23
24
25			`PAD_out`
26			`PAD`
27
28
29
30
31
32
33
34			`pad`
35
36
37
38
39
40			`pad_out`
41			`pad_out`
42
43
44			`pad_oe`
45			`pad_oe`
46
47
48
49
50
51
52
53
54	134	jt_eaton
55	131	jt_eaton
56	134	jt_eaton
57
58
59
60			`gen_verilog`
61			`104.0`
62			`none`
63			`common`
64			`./tools/verilog/gen_verilog`
65
66
67			`destination`
68			`pad_tri_dig`
69
70
71
72
73
74
75
76
77
78
79
80	131	jt_eaton
81
82
83	134	jt_eaton
84
85			`verilog`
86
87
88			`spirit:library="Testbench"`
89			`spirit:name="toolflow"`
90			`spirit:version="verilog"/>`
91
92
93
94
95
96	131	jt_eaton
97	134	jt_eaton	`commoncommon`
98			`Verilog`
99
100
101			`fs-common`
102
103
104
105
106
107
108	131	jt_eaton	`sim:Simulation:`
109			`Verilog`
110
111
112			`fs-sim`
113
114
115
116
117			`syn:Synthesis:`
118			`Verilog`
119
120
121			`fs-syn`
122
123
124
125
126
127			`doc`
128
129
130			`spirit:library="Testbench"`
131			`spirit:name="toolflow"`
132			`spirit:version="documentation"/>`
133
134			`:Documentation:`
135			`Verilog`
136
137
138
139
140
141
142
143
144
145
146			`PAD`
147			`wire`
148			`inout`
149
150
151			`pad_out`
152			`wire`
153			`in`
154
155
156			`pad_oe`
157			`wire`
158			`in`
159
160
161
162
163
164
165
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169
170	134	jt_eaton
171	131	jt_eaton
172
173	134	jt_eaton
174			`fs-common`
175	131	jt_eaton
176	134	jt_eaton
177
178			`../verilog/pad_tri_dig`
179			`verilogSourcefragment`
180
181	131	jt_eaton
182
183
184	134	jt_eaton
185
186
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194
195	131	jt_eaton
196			`fs-sim`
197
198	134	jt_eaton
199
200
201			`../verilog/copyright`
202			`verilogSourceinclude`
203
204
205
206
207
208			`../verilog/common/pad_tri_dig`
209			`verilogSourcemodule`
210
211
212
213
214
215	131	jt_eaton
216			`dest_dir`
217	134	jt_eaton	`../views/sim/`
218	131	jt_eaton	`verilogSourcelibraryDir`
219
220
221
222
223
224
225			`fs-syn`
226
227	134	jt_eaton
228
229			`../verilog/copyright`
230			`verilogSourceinclude`
231
232
233
234	131	jt_eaton
235	134	jt_eaton
236			`../verilog/common/pad_tri_dig`
237			`verilogSourcemodule`
238
239
240
241
242
243	131	jt_eaton	`dest_dir`
244	134	jt_eaton	`../views/syn/`
245	131	jt_eaton	`verilogSourcelibraryDir`
246
247
248
249
250
251
252
253
254
255			`fs-lint`
256
257			`dest_dir`
258	134	jt_eaton	`../views/syn/`
259	131	jt_eaton	`verilogSourcelibraryDir`
260
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