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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reg/] [rtl/] [verilog/] [logic_rst] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton
 
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always@(posedge clk or negedge reset_n)
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begin
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if(!reset_n)  Q <= 1'b0;
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else
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              Q <=  D;
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end
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