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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [verilog/] [reset_asyncdisable.v] - Blame information for rev 131

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module
cde_reset_asyncdisable
#(parameter    WIDTH = 1      )
(
   input  wire               reset,
   input  wire               reset_n,
   input  wire               atg_asyncdisable,
   input  wire [WIDTH - 1:0] sync_reset,
 
   output wire [WIDTH - 1:0] reset_n_out,
   output wire [WIDTH - 1:0] reset_out
);
 
assign  reset_out   =   sync_reset                                 | {WIDTH{reset}};
assign  reset_n_out = (~sync_reset    | {WIDTH{atg_asyncdisable}}) & {WIDTH{reset_n}};
 
endmodule
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`module`
2			`cde_reset_asyncdisable`
3			`#(parameter WIDTH = 1 )`
4			`(`
5			`input wire reset,`
6			`input wire reset_n,`
7			`input wire atg_asyncdisable,`
8			`input wire [WIDTH - 1:0] sync_reset,`
9
10			`output wire [WIDTH - 1:0] reset_n_out,`
11			`output wire [WIDTH - 1:0] reset_out`
12			`);`
13
14			`assign reset_out = sync_reset \| {WIDTH{reset}};`
15			`assign reset_n_out = (~sync_reset \| {WIDTH{atg_asyncdisable}}) & {WIDTH{reset_n}};`
16
17			`endmodule`
18

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [verilog/] [reset_asyncdisable.v] - Blame information for rev 131