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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [verilog/] [reset_def.v] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
module
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cde_reset_def
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#(parameter  WIDTH = 1,  // width of reset bus
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  parameter  DEPTH = 1   // depth of synchronizer
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 )(
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   input  clk,
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   input  async_reset_n,
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   input  atg_asyncdisable,
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   input  [WIDTH - 1:0] sync_reset,               // signals to control resets
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   output [WIDTH - 1:0] reset_n_out,              // Async reset
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   output [WIDTH - 1:0] reset_out                 // Sync reset
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);
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// ****************************************************************************
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// Reg declarations
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// ****************************************************************************
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wire  [WIDTH - 1:0]   reset_synced;
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  cde_sync_with_reset
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  #(.WIDTH  (WIDTH),
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    .DEPTH  (DEPTH),
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    .RST_VAL({WIDTH{1'b1}})
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   )
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  cde_1(
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    .clk                 (clk),
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    .reset_n             (async_reset_n),
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    .data_in             (sync_reset),
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    .data_out            (reset_synced)
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       );
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  cde_reset_asyncdisable
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   #(.WIDTH(WIDTH))
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  cde_2(
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    .reset               (1'b0),
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    .reset_n             (async_reset_n),
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    .atg_asyncdisable    (atg_asyncdisable),
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    .sync_reset          (reset_synced),
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    .reset_n_out         (reset_n_out),
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    .reset_out           (reset_out)
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     );
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endmodule
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