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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_asyncdisable.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
reset
asyncdisable  default
 
 
 
 

 
 
 
 
 
 

 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

WIDTH1

 

 
reset_n
wire
in

 
reset
wire
in

 
atg_asyncdisable
wire
in

 
 
 
sync_reset
wire
in
WIDTH-10

 
 
reset_n_out
wire
out
WIDTH-10

 
 
reset_out
wire
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`reset`
15			`asyncdisable default`
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36			`fs-sim`
37
38
39
40			`dest_dir`
41			`../verilog/`
42			`verilogSourcelibraryDir`
43
44
45
46
47
48
49			`fs-syn`
50
51
52			`dest_dir`
53			`../verilog/`
54			`verilogSourcelibraryDir`
55
56
57
58
59
60
61
62
63
64			`fs-lint`
65
66			`dest_dir`
67			`../verilog/`
68			`verilogSourcelibraryDir`
69
70
71
72
73
74
75
76
77
78
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81
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87			`sim:Simulation:`
88
89			`Verilog`
90
91
92			`fs-sim`
93
94
95
96
97			`syn:Synthesis:`
98
99			`Verilog`
100
101
102			`fs-syn`
103
104
105
106
107
108
109
110			`doc`
111
112
113			`spirit:library="Testbench"`
114			`spirit:name="toolflow"`
115			`spirit:version="documentation"/>`
116
117			`:Documentation:`
118			`Verilog`
119
120
121
122
123
124
125
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127
128
129			`WIDTH1`
130
131
132
133
134			`reset_n`
135			`wire`
136			`in`
137
138
139			`reset`
140			`wire`
141			`in`
142
143
144			`atg_asyncdisable`
145			`wire`
146			`in`
147
148
149
150
151			`sync_reset`
152			`wire`
153			`in`
154			`WIDTH-10`
155
156
157
158			`reset_n_out`
159			`wire`
160			`out`
161			`WIDTH-10`
162
163
164
165			`reset_out`
166			`wire`
167			`out`
168			`WIDTH-10`
169
170
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_asyncdisable.xml] - Blame information for rev 131