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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
reset
def  default
 
 
 

 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 

 
 
 
 
 
 

       
 
              
              Hierarchical
              
                                   spirit:library="cde"
                                   spirit:name="reset"
                                   spirit:version="def.design"/>
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

WIDTH1
DEPTH1

 

 
clk
wire
in

 
async_reset_n
wire
in

 
atg_asyncdisable
wire
in

 
sync_reset
wire
in
WIDTH-10

 
 
reset_n_out
wire
out
WIDTH-10

 
 
 
reset_out
wire
out
WIDTH-10

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`reset`
15			`def default`
16
17
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21
22
23
24
25
26
27
28
29
30
31
32
33			`fs-sim`
34
35
36
37			`dest_dir`
38			`../verilog/`
39			`verilogSourcelibraryDir`
40
41
42
43
44
45
46			`fs-syn`
47
48
49			`dest_dir`
50			`../verilog/`
51			`verilogSourcelibraryDir`
52
53
54
55
56
57
58
59
60
61			`fs-lint`
62
63			`dest_dir`
64			`../verilog/`
65			`verilogSourcelibraryDir`
66
67
68
69
70
71
72
73
74
75
76
77
78
79
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81
82
83			`Hierarchical`
84
85			`spirit:library="cde"`
86			`spirit:name="reset"`
87			`spirit:version="def.design"/>`
88
89
90
91
92			`sim:Simulation:`
93			`Verilog`
94
95
96			`fs-sim`
97
98
99
100
101			`syn:Synthesis:`
102			`Verilog`
103
104
105			`fs-syn`
106
107
108
109
110
111
112			`doc`
113
114
115			`spirit:library="Testbench"`
116			`spirit:name="toolflow"`
117			`spirit:version="documentation"/>`
118
119			`:Documentation:`
120			`Verilog`
121
122
123
124
125
126
127
128
129			`WIDTH1`
130			`DEPTH1`
131
132
133
134
135			`clk`
136			`wire`
137			`in`
138
139
140			`async_reset_n`
141			`wire`
142			`in`
143
144
145			`atg_asyncdisable`
146			`wire`
147			`in`
148
149
150			`sync_reset`
151			`wire`
152			`in`
153			`WIDTH-10`
154
155
156
157			`reset_n_out`
158			`wire`
159			`out`
160			`WIDTH-10`
161
162
163
164
165			`reset_out`
166			`wire`
167			`out`
168			`WIDTH-10`
169
170
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_def.xml] - Blame information for rev 133