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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [verilog/] [serial_rcvr] - Blame information for rev 134

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reg           [SIZE-1:0]  shift_cnt;
 
//
//   shift_cnt controls the serial bit out
//
//   0           Start bit
//   1-> WIDTH   Data bit lsb first
//   WIDTH+1     Parity bit if enabled
//   2^SIZE-1    Last stop bit and idle
 
always@(posedge clk)
  if( break_detect)
    begin
    shift_cnt       <= {SIZE{1'b1}};
    last_cnt        <= 1'b0;
    end
  else
  if(!edge_enable)
    begin
    shift_cnt       <= shift_cnt;
    last_cnt        <= 1'b0;
    end
  else
  if(( shift_cnt ==  {SIZE{1'b1}}))
   begin
    shift_cnt       <= {SIZE{1'b0}};
    last_cnt        <= 1'b0;
   end
  else
  if ( shift_cnt == WIDTH)
    case( parity_enable )
      (1'b0):
        begin
        shift_cnt   <= {SIZE{1'b1}};
        last_cnt    <= 1'b1;
        end
 
      (1'b1):
        begin
        shift_cnt   <= shift_cnt + 1'b1;
        last_cnt    <= 1'b0;
        end
   endcase // case (parity_enable)
  else
  if ( shift_cnt == (WIDTH+1))
     begin
     shift_cnt      <= {SIZE{1'b1}};
     last_cnt       <= 1'b1;
     end
  else
     begin
     shift_cnt      <= shift_cnt + 1'b1;
     last_cnt       <= 1'b0;
     end
//
//
//   load shift_buffer during start_bit
//   shift down every bit
//
//
always@(posedge clk)
  if(reset)                                                        shift_buffer <= {WIDTH{1'b0}};
  else
  if(!edge_enable)                                                 shift_buffer <= shift_buffer;
  else
  if(shift_cnt == {SIZE{1'b1}})                                    shift_buffer <= {WIDTH{1'b0}};
  else
  if(shift_cnt <= WIDTH-1 )                                        shift_buffer <= {ser_in,shift_buffer[WIDTH-1:1]};
  else                                                             shift_buffer <= shift_buffer;
//
//
//   calculate parity on the fly
//   seed reg with 0 for odd and 1 for even
//   force reg to 0 or 1 if needed
//
always@(posedge clk)
  if(reset)                                                        parity_calc <= 1'b0;
  else
  if(!edge_enable)                                                 parity_calc <= parity_calc;
  else
  if(parity_force || (shift_cnt == {SIZE{1'b1}}))                  parity_calc <= parity_type;
  else
  if(shift_cnt <= WIDTH-1 )                                        parity_calc <= parity_calc ^ ser_in;
  else                                                             parity_calc <= parity_calc;
//
//   sample parity bit and hold it until next start bit
//
always@(posedge clk)
  if(reset)                                                        parity_samp <= 1'b0;
  else
  if(!edge_enable)                                                 parity_samp <= parity_samp;
  else
  if(shift_cnt == {SIZE{1'b1}})                                    parity_samp <= 1'b0;
  else
  if(shift_cnt == WIDTH  )                                         parity_samp <= ser_in;
  else                                                             parity_samp <= parity_samp;
//
//   check for stop bit error
//
always@(posedge clk)
  if(reset)                                                        frame_err <= 1'b0;
  else
  if(!edge_enable)                                                 frame_err <= frame_err;
  else
  if(shift_cnt == {SIZE{1'b1}})                                    frame_err <= 1'b0;
  else
    begin
    case( parity_enable )
      (1'b0):
        begin
        if(shift_cnt == WIDTH    )                                       frame_err <= ser_in ^ STOP_VALUE;
        else                                                             frame_err <= frame_err;
        end
 
      (1'b1):
        begin
        if(shift_cnt == WIDTH+1  )                                       frame_err <= ser_in ^ STOP_VALUE;
        else                                                             frame_err <= frame_err;
        end
    endcase // case (parity_enable)
    end
 
 
 
 
 
 
 
 
 
 
//
//   create break_detect
//
always@(posedge clk)
  if(reset)                                                        break_detect  <= 1'b1;
  else
  if(BREAK)
    begin
    if(!break_detect)                                              break_detect  <= last_cnt && (ser_in ^ STOP_VALUE);
    else                                                           break_detect  <= (ser_in ^ STOP_VALUE);
    end
  else
    begin
                                                                   break_detect  <= 1'b0;
    end
 
 
 
 
 
always@(*)
  if(  shift_cnt ==  {SIZE{1'b1}})                                 stop_cnt   = 1'b1;
  else                                                             stop_cnt   = 1'b0;
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`reg [SIZE-1:0] shift_cnt;`
2
3			`//`
4			`// shift_cnt controls the serial bit out`
5			`//`
6			`// 0 Start bit`
7			`// 1-> WIDTH Data bit lsb first`
8			`// WIDTH+1 Parity bit if enabled`
9			`// 2^SIZE-1 Last stop bit and idle`
10
11			`always@(posedge clk)`
12			`if( break_detect)`
13			`begin`
14			`shift_cnt <= {SIZE{1'b1}};`
15			`last_cnt <= 1'b0;`
16			`end`
17			`else`
18			`if(!edge_enable)`
19			`begin`
20			`shift_cnt <= shift_cnt;`
21			`last_cnt <= 1'b0;`
22			`end`
23			`else`
24			`if(( shift_cnt == {SIZE{1'b1}}))`
25			`begin`
26			`shift_cnt <= {SIZE{1'b0}};`
27			`last_cnt <= 1'b0;`
28			`end`
29			`else`
30			`if ( shift_cnt == WIDTH)`
31			`case( parity_enable )`
32			`(1'b0):`
33			`begin`
34			`shift_cnt <= {SIZE{1'b1}};`
35			`last_cnt <= 1'b1;`
36			`end`
37
38			`(1'b1):`
39			`begin`
40			`shift_cnt <= shift_cnt + 1'b1;`
41			`last_cnt <= 1'b0;`
42			`end`
43			`endcase // case (parity_enable)`
44			`else`
45			`if ( shift_cnt == (WIDTH+1))`
46			`begin`
47			`shift_cnt <= {SIZE{1'b1}};`
48			`last_cnt <= 1'b1;`
49			`end`
50			`else`
51			`begin`
52			`shift_cnt <= shift_cnt + 1'b1;`
53			`last_cnt <= 1'b0;`
54			`end`
55			`//`
56			`//`
57			`// load shift_buffer during start_bit`
58			`// shift down every bit`
59			`//`
60			`//`
61			`always@(posedge clk)`
62			`if(reset) shift_buffer <= {WIDTH{1'b0}};`
63			`else`
64			`if(!edge_enable) shift_buffer <= shift_buffer;`
65			`else`
66			`if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= {WIDTH{1'b0}};`
67			`else`
68			`if(shift_cnt <= WIDTH-1 ) shift_buffer <= {ser_in,shift_buffer[WIDTH-1:1]};`
69			`else shift_buffer <= shift_buffer;`
70			`//`
71			`//`
72			`// calculate parity on the fly`
73			`// seed reg with 0 for odd and 1 for even`
74			`// force reg to 0 or 1 if needed`
75			`//`
76			`always@(posedge clk)`
77			`if(reset) parity_calc <= 1'b0;`
78			`else`
79			`if(!edge_enable) parity_calc <= parity_calc;`
80			`else`
81			`if(parity_force \|\| (shift_cnt == {SIZE{1'b1}})) parity_calc <= parity_type;`
82			`else`
83			`if(shift_cnt <= WIDTH-1 ) parity_calc <= parity_calc ^ ser_in;`
84			`else parity_calc <= parity_calc;`
85			`//`
86			`// sample parity bit and hold it until next start bit`
87			`//`
88			`always@(posedge clk)`
89			`if(reset) parity_samp <= 1'b0;`
90			`else`
91			`if(!edge_enable) parity_samp <= parity_samp;`
92			`else`
93			`if(shift_cnt == {SIZE{1'b1}}) parity_samp <= 1'b0;`
94			`else`
95			`if(shift_cnt == WIDTH ) parity_samp <= ser_in;`
96			`else parity_samp <= parity_samp;`
97			`//`
98			`// check for stop bit error`
99			`//`
100			`always@(posedge clk)`
101			`if(reset) frame_err <= 1'b0;`
102			`else`
103			`if(!edge_enable) frame_err <= frame_err;`
104			`else`
105			`if(shift_cnt == {SIZE{1'b1}}) frame_err <= 1'b0;`
106			`else`
107			`begin`
108			`case( parity_enable )`
109			`(1'b0):`
110			`begin`
111			`if(shift_cnt == WIDTH ) frame_err <= ser_in ^ STOP_VALUE;`
112			`else frame_err <= frame_err;`
113			`end`
114
115			`(1'b1):`
116			`begin`
117			`if(shift_cnt == WIDTH+1 ) frame_err <= ser_in ^ STOP_VALUE;`
118			`else frame_err <= frame_err;`
119			`end`
120			`endcase // case (parity_enable)`
121			`end`
122
123
124
125
126
127
128
129
130
131
132			`//`
133			`// create break_detect`
134			`//`
135			`always@(posedge clk)`
136			`if(reset) break_detect <= 1'b1;`
137			`else`
138			`if(BREAK)`
139			`begin`
140			`if(!break_detect) break_detect <= last_cnt && (ser_in ^ STOP_VALUE);`
141			`else break_detect <= (ser_in ^ STOP_VALUE);`
142			`end`
143			`else`
144			`begin`
145			`break_detect <= 1'b0;`
146			`end`
147
148
149
150
151
152			`always@(*)`
153			`if( shift_cnt == {SIZE{1'b1}}) stop_cnt = 1'b1;`
154			`else stop_cnt = 1'b0;`
155
156
157

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [verilog/] [serial_rcvr] - Blame information for rev 134