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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [verilog/] [serial_xmit] - Blame information for rev 134

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reg [SIZE-1:0]           shift_cnt;
reg [WIDTH-1:0]          shift_buffer;
reg                      parity_calc;
reg                      delayed_edge_enable;
 
 
//
//   shift_cnt controls the serial bit out
//
//   0           Start bit
//   1-> WIDTH   Data bit lsb first
//   WIDTH+1     Parity bit if enabled
//   2^SIZE-1    Last stop bit and idle
 
always@(posedge clk)
  if(reset || buffer_empty)                                        shift_cnt   <= {SIZE{1'b1}};
  else
  if(!edge_enable)                                                 shift_cnt   <= shift_cnt;
  else
  if(( shift_cnt ==  {SIZE{1'b1}}  ) &&  ! buffer_empty )          shift_cnt   <= {SIZE{1'b0}};
  else
  if ( shift_cnt == WIDTH)
    case(parity_enable)
      (1'b0):                                                      shift_cnt   <= {SIZE{1'b1}};
      (1'b1):                                                      shift_cnt   <= shift_cnt + 1'b1;
    endcase // case ({two_stop_enable,parity_enable})
  else
  if ( shift_cnt == (WIDTH+1))                                     shift_cnt   <= {SIZE{1'b1}};
  else                                                             shift_cnt   <= shift_cnt + 1'b1;
 
//
//
//   Clear buffer_empty upon load pulse
//   set it back at the start of the final stop pulse
//   if load happens BEFORE the next edge_enable then data transfer will have no pauses
//   logic ensures that having load happen on a edge_enable will work
//
 
always@(posedge clk)
   if(reset)                                                       delayed_edge_enable <= 1'b0;
   else                                                            delayed_edge_enable <= edge_enable && ! load;
 
 
always@(posedge clk)
if(reset)                                                          buffer_empty <= 1'b1;
else
if(load)                                                           buffer_empty <= 1'b0;
else
if((shift_cnt == {SIZE{1'b1}}) && delayed_edge_enable)
                                                                   buffer_empty <= 1'b1;
else                                                               buffer_empty <= buffer_empty;
 
 
 
 
 
//
//
//   load shift_buffer during start_bit
//   shift down every bit
//
//
always@(posedge clk)
  if(reset)                                                        shift_buffer <= {WIDTH{1'b0}};
  else
  if(load)                                                         shift_buffer <= data;
  else
  if(!edge_enable)                                                 shift_buffer <= shift_buffer;
  else
  if(shift_cnt == {SIZE{1'b1}})                                    shift_buffer <= shift_buffer;
  else
  if(shift_cnt == {SIZE{1'b0}})                                    shift_buffer <= shift_buffer;
  else                                                             shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]};
 
 
 
 
 
 
//
//
//   calculate parity on the fly
//   seed reg with 0 for odd and 1 for even
//   force reg to 0 or 1 if needed
//
always@(posedge clk)
  if(reset)                                                        parity_calc <= 1'b0;
  else
  if(!edge_enable)                                                 parity_calc <= parity_calc;
  else
  if(parity_force || (shift_cnt == {SIZE{1'b0}}))                  parity_calc <= parity_type;
  else                                                             parity_calc <= parity_calc ^ shift_buffer[0];
 
 
//   send start_bit,data,parity and stop  based on shift_cnt
 
 
   always@(posedge clk)
     if(reset)                                                     ser_out <= stop_value;
     else
     if( shift_cnt == {SIZE{1'b0}} )                               ser_out <= start_value;
     else
     if( shift_cnt == {SIZE{1'b1}} )                               ser_out <= stop_value;
     else
     if( shift_cnt == ({SIZE{1'b1}}+1'b1) )                        ser_out <= stop_value;
     else
     if( shift_cnt == (WIDTH+1) )                                  ser_out <= parity_calc;
     else                                                          ser_out <= shift_buffer[0];
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`reg [SIZE-1:0] shift_cnt;`
2			`reg [WIDTH-1:0] shift_buffer;`
3			`reg parity_calc;`
4			`reg delayed_edge_enable;`
5
6
7			`//`
8			`// shift_cnt controls the serial bit out`
9			`//`
10			`// 0 Start bit`
11			`// 1-> WIDTH Data bit lsb first`
12			`// WIDTH+1 Parity bit if enabled`
13			`// 2^SIZE-1 Last stop bit and idle`
14
15			`always@(posedge clk)`
16			`if(reset \|\| buffer_empty) shift_cnt <= {SIZE{1'b1}};`
17			`else`
18			`if(!edge_enable) shift_cnt <= shift_cnt;`
19			`else`
20			`if(( shift_cnt == {SIZE{1'b1}} ) && ! buffer_empty ) shift_cnt <= {SIZE{1'b0}};`
21			`else`
22			`if ( shift_cnt == WIDTH)`
23			`case(parity_enable)`
24			`(1'b0): shift_cnt <= {SIZE{1'b1}};`
25			`(1'b1): shift_cnt <= shift_cnt + 1'b1;`
26			`endcase // case ({two_stop_enable,parity_enable})`
27			`else`
28			`if ( shift_cnt == (WIDTH+1)) shift_cnt <= {SIZE{1'b1}};`
29			`else shift_cnt <= shift_cnt + 1'b1;`
30
31			`//`
32			`//`
33			`// Clear buffer_empty upon load pulse`
34			`// set it back at the start of the final stop pulse`
35			`// if load happens BEFORE the next edge_enable then data transfer will have no pauses`
36			`// logic ensures that having load happen on a edge_enable will work`
37			`//`
38
39			`always@(posedge clk)`
40			`if(reset) delayed_edge_enable <= 1'b0;`
41			`else delayed_edge_enable <= edge_enable && ! load;`
42
43
44			`always@(posedge clk)`
45			`if(reset) buffer_empty <= 1'b1;`
46			`else`
47			`if(load) buffer_empty <= 1'b0;`
48			`else`
49			`if((shift_cnt == {SIZE{1'b1}}) && delayed_edge_enable)`
50			`buffer_empty <= 1'b1;`
51			`else buffer_empty <= buffer_empty;`
52
53
54
55
56
57			`//`
58			`//`
59			`// load shift_buffer during start_bit`
60			`// shift down every bit`
61			`//`
62			`//`
63			`always@(posedge clk)`
64			`if(reset) shift_buffer <= {WIDTH{1'b0}};`
65			`else`
66			`if(load) shift_buffer <= data;`
67			`else`
68			`if(!edge_enable) shift_buffer <= shift_buffer;`
69			`else`
70			`if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= shift_buffer;`
71			`else`
72			`if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= shift_buffer;`
73			`else shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]};`
74
75
76
77
78
79
80			`//`
81			`//`
82			`// calculate parity on the fly`
83			`// seed reg with 0 for odd and 1 for even`
84			`// force reg to 0 or 1 if needed`
85			`//`
86			`always@(posedge clk)`
87			`if(reset) parity_calc <= 1'b0;`
88			`else`
89			`if(!edge_enable) parity_calc <= parity_calc;`
90			`else`
91			`if(parity_force \|\| (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type;`
92			`else parity_calc <= parity_calc ^ shift_buffer[0];`
93
94
95			`// send start_bit,data,parity and stop based on shift_cnt`
96
97
98			`always@(posedge clk)`
99			`if(reset) ser_out <= stop_value;`
100			`else`
101			`if( shift_cnt == {SIZE{1'b0}} ) ser_out <= start_value;`
102			`else`
103			`if( shift_cnt == {SIZE{1'b1}} ) ser_out <= stop_value;`
104			`else`
105			`if( shift_cnt == ({SIZE{1'b1}}+1'b1) ) ser_out <= stop_value;`
106			`else`
107			`if( shift_cnt == (WIDTH+1) ) ser_out <= parity_calc;`
108			`else ser_out <= shift_buffer[0];`
109
110
111
112
113
114

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [verilog/] [serial_xmit] - Blame information for rev 134