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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_rcvr.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
rcvr  default
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      serial_rcvr
    
  

 
 
 
 
 
 

 
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

WIDTH8
SIZE4
BREAK0
 

 

 
clk
wire
in

 
reset
wire
in

 
edge_enable
wire
in

 
parity_enable
wire
in

 
 
parity_type
wire
in

 
ser_in
wire
in

 
parity_force
wire
in

 
 
 
shift_buffer
reg
out
WIDTH-10

 
stop_cnt
reg
out

 
last_cnt
reg
out

 
parity_calc
reg
out

 
parity_samp
reg
out

 
 
 
frame_err
reg
out

 
 
break_detect
reg
out

 

 

 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/serial_rcvr
        verilogSourcefragment
      
 
    
 
 
 
 
   
      fs-sim
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr
        verilogSourcemodule
      
 
 
      
dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
 
      
        
        ../verilog/common/serial_rcvr
        verilogSourcemodule
      
 
 
 
      
dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 

 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_rcvr.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`rcvr default`
16
17
18
19
20
21
22	134	jt_eaton
23			`gen_verilog`
24			`104.0`
25			`none`
26			`common`
27			`./tools/verilog/gen_verilog`
28
29
30			`destination`
31			`serial_rcvr`
32
33
34
35	131	jt_eaton
36
37	134	jt_eaton
38
39
40
41	131	jt_eaton
42
43
44
45
46
47
48
49
50
51
52	134	jt_eaton	`verilog`
53
54
55			`spirit:library="Testbench"`
56			`spirit:name="toolflow"`
57			`spirit:version="verilog"/>`
58
59
60
61
62
63
64			`commoncommon`
65			`Verilog`
66
67
68			`fs-common`
69
70
71
72
73
74
75	131	jt_eaton	`sim:Simulation:`
76			`Verilog`
77
78
79			`fs-sim`
80
81
82
83
84			`syn:Synthesis:`
85			`Verilog`
86
87
88			`fs-syn`
89
90
91
92
93
94
95			`doc`
96
97
98			`spirit:library="Testbench"`
99			`spirit:name="toolflow"`
100			`spirit:version="documentation"/>`
101
102			`:Documentation:`
103			`Verilog`
104
105
106
107
108
109
110
111
112
113			`WIDTH8`
114			`SIZE4`
115			`BREAK0`
116
117
118
119
120
121			`clk`
122			`wire`
123			`in`
124
125
126			`reset`
127			`wire`
128			`in`
129
130
131			`edge_enable`
132			`wire`
133			`in`
134
135
136			`parity_enable`
137			`wire`
138			`in`
139
140
141
142			`parity_type`
143			`wire`
144			`in`
145
146
147			`ser_in`
148			`wire`
149			`in`
150
151
152			`parity_force`
153			`wire`
154			`in`
155
156
157
158
159			`shift_buffer`
160			`reg`
161			`out`
162			`WIDTH-10`
163
164
165			`stop_cnt`
166			`reg`
167			`out`
168
169
170			`last_cnt`
171			`reg`
172			`out`
173
174
175			`parity_calc`
176			`reg`
177			`out`
178
179
180			`parity_samp`
181			`reg`
182			`out`
183
184
185	134	jt_eaton
186
187	131	jt_eaton	`frame_err`
188			`reg`
189			`out`
190
191
192
193	134	jt_eaton	`break_detect`
194			`reg`
195			`out`
196
197
198	131	jt_eaton
199
200
201
202
203
204
205
206
207
208	134	jt_eaton
209
210	131	jt_eaton
211	134	jt_eaton	`fs-common`
212
213
214
215			`../verilog/serial_rcvr`
216			`verilogSourcefragment`
217
218
219
220
221
222
223
224
225	131	jt_eaton	`fs-sim`
226
227	134	jt_eaton
228
229			`../verilog/copyright`
230			`verilogSourceinclude`
231
232	131	jt_eaton
233
234	134	jt_eaton
235			`../verilog/common/serial_rcvr`
236			`verilogSourcemodule`
237
238
239
240
241	131	jt_eaton	`dest_dir`
242	134	jt_eaton	`../views/sim/`
243	131	jt_eaton	`verilogSourcelibraryDir`
244
245
246
247
248
249
250			`fs-syn`
251
252	134	jt_eaton
253
254			`../verilog/copyright`
255			`verilogSourceinclude`
256
257
258
259
260
261	131	jt_eaton
262	134	jt_eaton
263			`../verilog/common/serial_rcvr`
264			`verilogSourcemodule`
265
266
267
268
269
270	131	jt_eaton	`dest_dir`
271	134	jt_eaton	`../views/syn/`
272	131	jt_eaton	`verilogSourcelibraryDir`
273
274
275
276
277
278
279
280
281
282			`fs-lint`
283
284	134	jt_eaton	`dest_dir../views/syn/`
285	131	jt_eaton	`verilogSourcelibraryDir`
286
287
288
289
290
291
292
293
294