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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_xmit.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
xmit  default
 
 

 
 
 
 
 

 
 
 
 
 
 
 

       
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 
 

WIDTH8

 
 
 

 
clk
wire
in

 
reset
wire
in

 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
load
wire
in

 
start_value
wire
in

 
stop_value
wire
in

 
 
 
data
wire
in
WIDTH-10

 
 
buffer_empty
reg
out

 
 
ser_out
reg
out

 
 
 
 

 

 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_xmit.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
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6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`xmit default`
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35			`sim:Simulation:`
36			`Verilog`
37
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39			`fs-sim`
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44			`syn:Synthesis:`
45			`Verilog`
46
47
48			`fs-syn`
49
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53			`doc`
54
55
56			`spirit:library="Testbench"`
57			`spirit:name="toolflow"`
58			`spirit:version="documentation"/>`
59
60			`:Documentation:`
61			`Verilog`
62
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73			`WIDTH8`
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80			`clk`
81			`wire`
82			`in`
83
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85			`reset`
86			`wire`
87			`in`
88
89
90			`edge_enable`
91			`wire`
92			`in`
93
94
95			`parity_enable`
96			`wire`
97			`in`
98
99
100			`parity_type`
101			`wire`
102			`in`
103
104
105			`parity_force`
106			`wire`
107			`in`
108
109
110			`load`
111			`wire`
112			`in`
113
114
115			`start_value`
116			`wire`
117			`in`
118
119
120			`stop_value`
121			`wire`
122			`in`
123
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127			`data`
128			`wire`
129			`in`
130			`WIDTH-10`
131
132
133
134			`buffer_empty`
135			`reg`
136			`out`
137
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140			`ser_out`
141			`reg`
142			`out`
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160			`fs-sim`
161
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164			`dest_dir`
165			`../verilog/`
166			`verilogSourcelibraryDir`
167
168
169
170
171
172
173			`fs-syn`
174
175
176			`dest_dir`
177			`../verilog/`
178			`verilogSourcelibraryDir`
179
180
181
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184
185
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187
188			`fs-lint`
189
190			`dest_dir../verilog/`
191			`verilogSourcelibraryDir`
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