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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_xmit.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
xmit  default
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      serial_xmit
    
  

 
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 
 

WIDTH8

 
 
 

 
clk
wire
in

 
reset
wire
in

 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
load
wire
in

 
start_value
wire
in

 
stop_value
wire
in

 
 
 
data
wire
in
WIDTH-10

 
 
buffer_empty
reg
out

 
 
ser_out
reg
out

 
 
 
 

 

 
 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/serial_xmit
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/serial_xmit
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/serial_xmit
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_xmit.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`xmit default`
16
17
18
19
20	134	jt_eaton
21			`gen_verilog`
22			`104.0`
23			`none`
24			`common`
25			`./tools/verilog/gen_verilog`
26
27
28			`destination`
29			`serial_xmit`
30
31
32
33	131	jt_eaton
34
35
36
37	134	jt_eaton
38
39	131	jt_eaton
40
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49	134	jt_eaton
50
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52
53	131	jt_eaton
54	134	jt_eaton	`verilog`
55
56
57			`spirit:library="Testbench"`
58			`spirit:name="toolflow"`
59			`spirit:version="verilog"/>`
60
61
62
63
64
65
66			`commoncommon`
67			`Verilog`
68
69
70			`fs-common`
71
72
73
74
75
76
77
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80
81
82	131	jt_eaton	`sim:Simulation:`
83			`Verilog`
84
85
86			`fs-sim`
87
88
89
90
91			`syn:Synthesis:`
92			`Verilog`
93
94
95			`fs-syn`
96
97
98
99
100			`doc`
101
102
103			`spirit:library="Testbench"`
104			`spirit:name="toolflow"`
105			`spirit:version="documentation"/>`
106
107			`:Documentation:`
108			`Verilog`
109
110
111
112
113
114
115
116
117
118
119
120			`WIDTH8`
121
122
123
124
125
126
127			`clk`
128			`wire`
129			`in`
130
131
132			`reset`
133			`wire`
134			`in`
135
136
137			`edge_enable`
138			`wire`
139			`in`
140
141
142			`parity_enable`
143			`wire`
144			`in`
145
146
147			`parity_type`
148			`wire`
149			`in`
150
151
152			`parity_force`
153			`wire`
154			`in`
155
156
157			`load`
158			`wire`
159			`in`
160
161
162			`start_value`
163			`wire`
164			`in`
165
166
167			`stop_value`
168			`wire`
169			`in`
170
171
172
173
174			`data`
175			`wire`
176			`in`
177			`WIDTH-10`
178
179
180
181			`buffer_empty`
182			`reg`
183			`out`
184
185
186
187			`ser_out`
188			`reg`
189			`out`
190
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204
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206	134	jt_eaton
207
208	131	jt_eaton
209	134	jt_eaton	`fs-common`
210
211
212
213			`../verilog/serial_xmit`
214			`verilogSourcefragment`
215
216
217
218
219
220
221	131	jt_eaton	`fs-sim`
222
223	134	jt_eaton
224
225
226			`../verilog/copyright`
227			`verilogSourceinclude`
228
229
230	131	jt_eaton
231
232	134	jt_eaton
233			`../verilog/common/serial_xmit`
234			`verilogSourcemodule`
235
236
237
238
239
240	131	jt_eaton	`dest_dir`
241	134	jt_eaton	`../views/sim/`
242	131	jt_eaton	`verilogSourcelibraryDir`
243
244
245
246
247
248
249			`fs-syn`
250
251	134	jt_eaton
252
253
254			`../verilog/copyright`
255			`verilogSourceinclude`
256
257
258
259	131	jt_eaton
260	134	jt_eaton
261			`../verilog/common/serial_xmit`
262			`verilogSourcemodule`
263
264
265
266
267
268	131	jt_eaton	`dest_dir`
269	134	jt_eaton	`../views/syn/`
270	131	jt_eaton	`verilogSourcelibraryDir`
271
272
273
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275
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277
278
279
280			`fs-lint`
281
282			`dest_dir../verilog/`
283			`verilogSourcelibraryDir`
284
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