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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_both_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
both_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      both.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 
 
 

 
       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="serial"
                                   spirit:version="both_dut.params"/>
              
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
      
 
 
 
 

 
 
 

 
 
 
   
      fs-common
 
 
 
      
        
        ../verilog/both.tb
        verilogSourcefragment
      
 
   
 
 
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/both.tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/common/both.tb
        verilogSourcemodule
      
 
 
 
 
 
   
 
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`both_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33			`both.tb`
34
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
42
43
44
45
46
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51
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62			`Params`
63
64
65			`spirit:library="cde"`
66			`spirit:name="serial"`
67			`spirit:version="both_dut.params"/>`
68
69
70
71
72
73
74			`icarus`
75
76
77			`spirit:library="Testbench"`
78			`spirit:name="toolflow"`
79			`spirit:version="icarus"/>`
80
81
82
83
84
85
86
87			`commoncommon`
88			`Verilog`
89
90
91			`fs-common`
92
93
94
95
96
97			`sim:Simulation:`
98			`Verilog`
99
100
101			`fs-sim`
102
103
104
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106
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108			`lint:Lint:`
109			`Verilog`
110
111
112			`fs-lint`
113
114
115
116
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119
120
121
122
123
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133
134			`fs-common`
135
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139
140			`../verilog/both.tb`
141			`verilogSourcefragment`
142
143
144
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146
147
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149
150
151
152			`fs-sim`
153
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157
158			`../verilog/common/both.tb`
159			`verilogSourcemodule`
160
161
162
163
164
165
166
167			`fs-lint`
168
169
170
171			`../verilog/common/both.tb`
172			`verilogSourcemodule`
173
174
175
176
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_both_tb.xml] - Blame information for rev 131