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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_both_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
both_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      serial_both_tb
    
  

 
 
 

 
 
 
 
 
 
 
 
 

 
       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="serial"
                                   spirit:version="both_dut.params"/>
              
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
      
 
 
 
 

 
 
 

 
 
 
   
      fs-common
 
 
 
      
        
        ../verilog/both.tb
        verilogSourcefragment
      
 
   
 
 
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/serial_both_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/common/serial_both_tb
        verilogSourcemodule
      
 
 
 
 
 
   
 
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`both_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	134	jt_eaton	`serial_both_tb`
34	131	jt_eaton
35
36
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55			`Params`
56
57
58			`spirit:library="cde"`
59			`spirit:name="serial"`
60			`spirit:version="both_dut.params"/>`
61
62
63
64
65
66
67			`icarus`
68
69
70			`spirit:library="Testbench"`
71			`spirit:name="toolflow"`
72			`spirit:version="icarus"/>`
73
74
75
76
77
78
79
80			`commoncommon`
81			`Verilog`
82
83
84			`fs-common`
85
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88
89
90			`sim:Simulation:`
91			`Verilog`
92
93
94			`fs-sim`
95
96
97
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99
100
101			`lint:Lint:`
102			`Verilog`
103
104
105			`fs-lint`
106
107
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127			`fs-common`
128
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132
133			`../verilog/both.tb`
134			`verilogSourcefragment`
135
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143
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145			`fs-sim`
146
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151	134	jt_eaton	`../verilog/common/serial_both_tb`
152	131	jt_eaton	`verilogSourcemodule`
153
154
155
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158
159
160			`fs-lint`
161
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164	134	jt_eaton	`../verilog/common/serial_both_tb`
165	131	jt_eaton	`verilogSourcemodule`
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_both_tb.xml] - Blame information for rev 134